Hi Brad, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on linuxtv-media/master] [also build test WARNING on v5.5 next-20200203] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Brad-Love/m88ds3103-Add-support-for-Montage-3103b-DVB-S-demod/20200203-135639 base: git://linuxtv.org/media_tree.git master config: i386-randconfig-b001-20200202 (attached as .config) compiler: gcc-7 (Debian 7.5.0-3) 7.5.0 reproduce: # save the attached .config to linux build tree make ARCH=i386 If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@xxxxxxxxx> All warnings (new ones prefixed by >>): drivers/media/dvb-frontends/m88ds3103.c: In function 'm88ds3103_set_frontend': >> drivers/media/dvb-frontends/m88ds3103.c:906:6: warning: this statement may fall through [-Wimplicit-fallthrough=] if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { ^ drivers/media/dvb-frontends/m88ds3103.c:911:2: note: here default: ^~~~~~~ vim +906 drivers/media/dvb-frontends/m88ds3103.c 623 624 static int m88ds3103_set_frontend(struct dvb_frontend *fe) 625 { 626 struct m88ds3103_dev *dev = fe->demodulator_priv; 627 struct i2c_client *client = dev->client; 628 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 629 int ret, len; 630 const struct m88ds3103_reg_val *init; 631 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */ 632 u8 buf[3]; 633 u16 u16tmp; 634 u32 tuner_frequency_khz, target_mclk, u32tmp; 635 s32 s32tmp; 636 static const struct reg_sequence reset_buf[] = { 637 {0x07, 0x80}, {0x07, 0x00} 638 }; 639 640 dev_dbg(&client->dev, 641 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", 642 c->delivery_system, c->modulation, c->frequency, c->symbol_rate, 643 c->inversion, c->pilot, c->rolloff); 644 645 if (!dev->warm) { 646 ret = -EAGAIN; 647 goto err; 648 } 649 650 /* reset */ 651 ret = regmap_multi_reg_write(dev->regmap, reset_buf, 2); 652 if (ret) 653 goto err; 654 655 /* Disable demod clock path */ 656 if (dev->chip_id == M88RS6000_CHIP_ID) { 657 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 658 ret = regmap_read(dev->regmap, 0xb2, &u32tmp); 659 if (ret) 660 goto err; 661 if (u32tmp == 0x01) { 662 ret = regmap_write(dev->regmap, 0x00, 0x00); 663 if (ret) 664 goto err; 665 ret = regmap_write(dev->regmap, 0xb2, 0x00); 666 if (ret) 667 goto err; 668 } 669 } 670 671 ret = regmap_write(dev->regmap, 0x06, 0xe0); 672 if (ret) 673 goto err; 674 } 675 676 /* program tuner */ 677 if (fe->ops.tuner_ops.set_params) { 678 ret = fe->ops.tuner_ops.set_params(fe); 679 if (ret) 680 goto err; 681 } 682 683 if (fe->ops.tuner_ops.get_frequency) { 684 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency_khz); 685 if (ret) 686 goto err; 687 } else { 688 /* 689 * Use nominal target frequency as tuner driver does not provide 690 * actual frequency used. Carrier offset calculation is not 691 * valid. 692 */ 693 tuner_frequency_khz = c->frequency; 694 } 695 696 /* set M88RS6000/DS3103B demod main mclk and ts mclk from tuner die */ 697 if (dev->chip_id == M88RS6000_CHIP_ID) { 698 if (c->symbol_rate > 45010000) 699 dev->mclk = 110250000; 700 else 701 dev->mclk = 96000000; 702 703 if (c->delivery_system == SYS_DVBS) 704 target_mclk = 96000000; 705 else 706 target_mclk = 144000000; 707 708 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 709 m88ds3103b_select_mclk(dev); 710 m88ds3103b_set_mclk(dev, target_mclk / 1000); 711 } 712 713 /* Enable demod clock path */ 714 ret = regmap_write(dev->regmap, 0x06, 0x00); 715 if (ret) 716 goto err; 717 usleep_range(10000, 20000); 718 } else { 719 /* set M88DS3103 mclk and ts mclk. */ 720 dev->mclk = 96000000; 721 722 switch (dev->cfg->ts_mode) { 723 case M88DS3103_TS_SERIAL: 724 case M88DS3103_TS_SERIAL_D7: 725 target_mclk = dev->cfg->ts_clk; 726 break; 727 case M88DS3103_TS_PARALLEL: 728 case M88DS3103_TS_CI: 729 if (c->delivery_system == SYS_DVBS) 730 target_mclk = 96000000; 731 else { 732 if (c->symbol_rate < 18000000) 733 target_mclk = 96000000; 734 else if (c->symbol_rate < 28000000) 735 target_mclk = 144000000; 736 else 737 target_mclk = 192000000; 738 } 739 break; 740 default: 741 dev_dbg(&client->dev, "invalid ts_mode\n"); 742 ret = -EINVAL; 743 goto err; 744 } 745 746 switch (target_mclk) { 747 case 96000000: 748 u8tmp1 = 0x02; /* 0b10 */ 749 u8tmp2 = 0x01; /* 0b01 */ 750 break; 751 case 144000000: 752 u8tmp1 = 0x00; /* 0b00 */ 753 u8tmp2 = 0x01; /* 0b01 */ 754 break; 755 case 192000000: 756 u8tmp1 = 0x03; /* 0b11 */ 757 u8tmp2 = 0x00; /* 0b00 */ 758 break; 759 } 760 ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6); 761 if (ret) 762 goto err; 763 ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6); 764 if (ret) 765 goto err; 766 } 767 768 ret = regmap_write(dev->regmap, 0xb2, 0x01); 769 if (ret) 770 goto err; 771 772 ret = regmap_write(dev->regmap, 0x00, 0x01); 773 if (ret) 774 goto err; 775 776 switch (c->delivery_system) { 777 case SYS_DVBS: 778 if (dev->chip_id == M88RS6000_CHIP_ID) { 779 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals); 780 init = m88rs6000_dvbs_init_reg_vals; 781 } else { 782 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals); 783 init = m88ds3103_dvbs_init_reg_vals; 784 } 785 break; 786 case SYS_DVBS2: 787 if (dev->chip_id == M88RS6000_CHIP_ID) { 788 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals); 789 init = m88rs6000_dvbs2_init_reg_vals; 790 } else { 791 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals); 792 init = m88ds3103_dvbs2_init_reg_vals; 793 } 794 break; 795 default: 796 dev_dbg(&client->dev, "invalid delivery_system\n"); 797 ret = -EINVAL; 798 goto err; 799 } 800 801 /* program init table */ 802 if (c->delivery_system != dev->delivery_system) { 803 ret = m88ds3103_wr_reg_val_tab(dev, init, len); 804 if (ret) 805 goto err; 806 } 807 808 if (dev->chip_id == M88RS6000_CHIP_ID) { 809 if (c->delivery_system == SYS_DVBS2 && 810 c->symbol_rate <= 5000000) { 811 ret = regmap_write(dev->regmap, 0xc0, 0x04); 812 if (ret) 813 goto err; 814 buf[0] = 0x09; 815 buf[1] = 0x22; 816 buf[2] = 0x88; 817 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3); 818 if (ret) 819 goto err; 820 } 821 ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08); 822 if (ret) 823 goto err; 824 825 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 826 buf[0] = m88ds3103b_dt_read(dev, 0x15); 827 buf[1] = m88ds3103b_dt_read(dev, 0x16); 828 829 if (c->symbol_rate > 45010000) { 830 buf[0] &= ~0x03; 831 buf[0] |= 0x02; 832 buf[0] |= ((147 - 32) >> 8) & 0x01; 833 buf[1] = (147 - 32) & 0xFF; 834 835 dev->mclk = 110250 * 1000; 836 } else { 837 buf[0] &= ~0x03; 838 buf[0] |= ((128 - 32) >> 8) & 0x01; 839 buf[1] = (128 - 32) & 0xFF; 840 841 dev->mclk = 96000 * 1000; 842 } 843 m88ds3103b_dt_write(dev, 0x15, buf[0]); 844 m88ds3103b_dt_write(dev, 0x16, buf[1]); 845 846 regmap_read(dev->regmap, 0x30, &u32tmp); 847 u32tmp &= ~0x80; 848 regmap_write(dev->regmap, 0x30, u32tmp & 0xff); 849 } 850 851 ret = regmap_write(dev->regmap, 0xf1, 0x01); 852 if (ret) 853 goto err; 854 855 if (dev->chiptype != M88DS3103_CHIPTYPE_3103B) { 856 ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80); 857 if (ret) 858 goto err; 859 } 860 } 861 862 switch (dev->cfg->ts_mode) { 863 case M88DS3103_TS_SERIAL: 864 u8tmp1 = 0x00; 865 u8tmp = 0x06; 866 break; 867 case M88DS3103_TS_SERIAL_D7: 868 u8tmp1 = 0x20; 869 u8tmp = 0x06; 870 break; 871 case M88DS3103_TS_PARALLEL: 872 u8tmp = 0x02; 873 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 874 u8tmp = 0x01; 875 u8tmp1 = 0x01; 876 } 877 break; 878 case M88DS3103_TS_CI: 879 u8tmp = 0x03; 880 break; 881 default: 882 dev_dbg(&client->dev, "invalid ts_mode\n"); 883 ret = -EINVAL; 884 goto err; 885 } 886 887 if (dev->cfg->ts_clk_pol) 888 u8tmp |= 0x40; 889 890 /* TS mode */ 891 ret = regmap_write(dev->regmap, 0xfd, u8tmp); 892 if (ret) 893 goto err; 894 895 switch (dev->cfg->ts_mode) { 896 case M88DS3103_TS_SERIAL: 897 case M88DS3103_TS_SERIAL_D7: 898 ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1); 899 if (ret) 900 goto err; 901 u16tmp = 0; 902 u8tmp1 = 0x3f; 903 u8tmp2 = 0x3f; 904 break; 905 case M88DS3103_TS_PARALLEL: > 906 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 907 ret = m88ds3103_update_bits(dev, 0x29, 0x01, u8tmp1); 908 if (ret) 909 goto err; 910 } 911 default: 912 u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk); 913 u8tmp1 = u16tmp / 2 - 1; 914 u8tmp2 = DIV_ROUND_UP(u16tmp, 2) - 1; 915 } 916 917 dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n", 918 target_mclk, dev->cfg->ts_clk, u16tmp); 919 920 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */ 921 /* u8tmp2[5:0] => ea[5:0] */ 922 u8tmp = (u8tmp1 >> 2) & 0x0f; 923 ret = regmap_update_bits(dev->regmap, 0xfe, 0x0f, u8tmp); 924 if (ret) 925 goto err; 926 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0; 927 ret = regmap_write(dev->regmap, 0xea, u8tmp); 928 if (ret) 929 goto err; 930 931 if (c->symbol_rate <= 3000000) 932 u8tmp = 0x20; 933 else if (c->symbol_rate <= 10000000) 934 u8tmp = 0x10; 935 else 936 u8tmp = 0x06; 937 938 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) 939 m88ds3103b_set_mclk(dev, target_mclk / 1000); 940 941 ret = regmap_write(dev->regmap, 0xc3, 0x08); 942 if (ret) 943 goto err; 944 945 ret = regmap_write(dev->regmap, 0xc8, u8tmp); 946 if (ret) 947 goto err; 948 949 ret = regmap_write(dev->regmap, 0xc4, 0x08); 950 if (ret) 951 goto err; 952 953 ret = regmap_write(dev->regmap, 0xc7, 0x00); 954 if (ret) 955 goto err; 956 957 u16tmp = DIV_ROUND_CLOSEST_ULL((u64)c->symbol_rate * 0x10000, dev->mclk); 958 buf[0] = (u16tmp >> 0) & 0xff; 959 buf[1] = (u16tmp >> 8) & 0xff; 960 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2); 961 if (ret) 962 goto err; 963 964 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1); 965 if (ret) 966 goto err; 967 968 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4); 969 if (ret) 970 goto err; 971 972 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc); 973 if (ret) 974 goto err; 975 976 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 977 /* enable/disable 192M LDPC clock */ 978 ret = m88ds3103_update_bits(dev, 0x29, 0x10, 979 (c->delivery_system == SYS_DVBS) ? 0x10 : 0x0); 980 if (ret) 981 goto err; 982 983 ret = m88ds3103_update_bits(dev, 0xc9, 0x08, 0x08); 984 } 985 986 dev_dbg(&client->dev, "carrier offset=%d\n", 987 (tuner_frequency_khz - c->frequency)); 988 989 /* Use 32-bit calc as there is no s64 version of DIV_ROUND_CLOSEST() */ 990 s32tmp = 0x10000 * (tuner_frequency_khz - c->frequency); 991 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk / 1000); 992 buf[0] = (s32tmp >> 0) & 0xff; 993 buf[1] = (s32tmp >> 8) & 0xff; 994 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2); 995 if (ret) 996 goto err; 997 998 ret = regmap_write(dev->regmap, 0x00, 0x00); 999 if (ret) 1000 goto err; 1001 1002 ret = regmap_write(dev->regmap, 0xb2, 0x00); 1003 if (ret) 1004 goto err; 1005 1006 dev->delivery_system = c->delivery_system; 1007 1008 return 0; 1009 err: 1010 dev_dbg(&client->dev, "failed=%d\n", ret); 1011 return ret; 1012 } 1013 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx Intel Corporation
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.config.gz
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