Hi Fabio, On Thu, Apr 19, 2018 at 7:08 PM, Fabio Estevam <festevam@xxxxxxxxx> wrote: > On Thu, Apr 19, 2018 at 1:55 PM, Ibtsam Ul-Haq > <ibtsam.haq.0x01@xxxxxxxxx> wrote: > >> I can see by using a logic analyzer that the PIXCLK does not look >> nice. It looks similar to the issue mentioned here: >> https://community.nxp.com/thread/454467 >> >> except that in my case it looks pulled up instead of down. >> However I do not yet have a clue what causes this. >> VSYNC and HSYNC waveforms look ok, until the whole capture is stopped >> due to the error, after 14 frames. >> The relevant pinctrl settings in the dts are: >> >> MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x4001b0b0 >> MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x4001b0b0 >> MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x4001b0b0 > > Not sure why you are setting the SION bit (bit 30) on the CSI pads. > > Does it work better if you do not set it? > Thanks for your response. The SION bit was this way in the dts provided by the board manufacturer. But now I have tried it with the SION bit cleared, unfortunately it didn't make any difference. There is a new board revision coming soon with several layout changes. So currently I am waiting, in the hope that we don't waste time debugging it if it were a hardware problem. > For your reference: this is what we do on imx6qdl-sabresd.dtsi: > > MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 > MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 > MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 > MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 > MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 > MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 > MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 > MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 > MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 > MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 > MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 Best regards, Ibtsam Haq
