On Thu, Jul 6, 2017 at 11:02 PM, Arnd Bergmann <arnd@xxxxxxxx> wrote: > On Thu, Jul 6, 2017 at 3:49 PM, Tomasz Figa <tfiga@xxxxxxxxxxxx> wrote: >> On Thu, Jul 6, 2017 at 10:31 PM, Tomasz Figa <tfiga@xxxxxxxxxxxx> wrote: > >>> On the other hand, if it's strictly about base/dma-mapping, we might >>> not need it indeed. The driver could call iommu-dma helpers directly, >>> without the need to provide its own DMA ops. One caveat, though, we >>> are not able to obtain coherent (i.e. uncached) memory with this >>> approach, which might have some performance effects and complicates >>> the code, that would now need to flush caches even for some small >>> internal buffers. >> >> I think I should add a bit of explanation here: >> 1) the device is non-coherent with CPU caches, even on x86, >> 2) it looks like x86 does not have non-coherent DMA ops, (but it >> might be something that could be fixed) > > I don't understand what this means here. The PCI on x86 is always > cache-coherent, so why is the device not? > > Do you mean that the device has its own caches that may need > flushing to make the device cache coherent with the CPU cache, > rather than flushing the CPU caches? Sakari might be able to explain this with more technical details, but generally the device is not a standard PCI device one might find on existing x86 systems. It is some kind of embedded subsystem that behaves mostly like a PCI device, with certain exceptions, one being the lack of coherency with CPU caches, at least for certain parts of the subsystem. The reference vendor code disables the coherency completely, for reasons not known to me, but AFAICT this is the preferred operating mode, possibly due to performance effects (this is a memory-heavy image processing subsystem). Best regards, Tomasz
