Hi Alan, On Thu, Jun 8, 2017 at 2:45 AM, Alan Cox <gnomes@xxxxxxxxxxxxxxxxxxx> wrote: >> > + struct ipu3_mmu *mmu = to_ipu3_mmu(dev); >> > + dma_addr_t daddr = iommu_iova_to_phys(mmu->domain, dma_handle); >> > + >> > + clflush_cache_range(phys_to_virt(daddr), size); >> >> You might need to consider another IOMMU on the way here. Generally, >> given that daddr is your MMU DMA address (not necessarily CPU physical >> address), you should be able to call >> >> dma_sync_single_for_cpu(<your pci device>, daddr, size, dir) > > Te system IOMMU (if enabled) may be cache coherent - and on x86 would be, > so it doesn't think it needs to do anything for cache synchronization > and the dma_sync won't actually do any work. I'm not very familiar with x86, but typically I found coherency to be an attribute of the DMA master (i.e. if it is connected to a coherent memory port). Looking at all the IPU3 code, it looks like the whole PCI device is non-coherent for some reason (e.g. you can see implicit cache flushes for page tables). So I would have expected that a non-coherent variant of x86 dma_ops is used for the PCI struct device, which would do cache maintenance in its dma_sync_* ops. Best regards, Tomasz
