> > + struct ipu3_mmu *mmu = to_ipu3_mmu(dev); > > + dma_addr_t daddr = iommu_iova_to_phys(mmu->domain, dma_handle); > > + > > + clflush_cache_range(phys_to_virt(daddr), size); > > You might need to consider another IOMMU on the way here. Generally, > given that daddr is your MMU DMA address (not necessarily CPU physical > address), you should be able to call > > dma_sync_single_for_cpu(<your pci device>, daddr, size, dir) Te system IOMMU (if enabled) may be cache coherent - and on x86 would be, so it doesn't think it needs to do anything for cache synchronization and the dma_sync won't actually do any work. Alan
