On Fri, Aug 07, 2009 at 08:15:01AM -0500, Robin Holt wrote: > On Fri, Aug 07, 2009 at 02:07:43PM +0200, Laurent Desnogues wrote: > > On Fri, Aug 7, 2009 at 11:54 AM, Jamie Lokier<jamie@xxxxxxxxxxxxx> wrote: > > > > > > 1. Does the architecture not prevent speculative instruction > > > prefetches from crossing a page boundary? It would be handy under the > > > circumstances. > > > > There's no such restriction in ARMv7 architecture. > > Doesn't it prevent them for uncached areas? "Uncached areas" is very very fuzzy. Are you talking about a non-cachable memory mapping, or a strongly ordered mapping. I'm afraid that we're going to have to require more precise use of language to describe these things - wolley statements like "uncached areas" are now just too ambiguous. > I _THOUGHT_ there was an > alloc_consistent (or something like that) call on ARM which gave you > an uncached mapping where you could do DMA. The dma_alloc_coherent() does _remap_ memory into a strongly ordered mapping. However, the fully cached mapping remains, which means that the CPU can still speculatively prefetch from that memory. Since we map the fully cached mapping using section (or even supersection) mappings for TLB efficiency, we can't change the memory type on a per-page basis. > I also thought there was a dma_* set of functions which remapped as > uncached before DMA begins and remapped as normal after DMA has been > completed. You're talking about the deprecated DMA bounce code there. It's basically the same problem since it uses the dma_alloc_coherent() interface to gain a source of DMA-able memory. -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
