Hi Robert,
On Wed, 4 Mar 2009, Robert Jarzmik wrote:
> Guennadi Liakhovetski <g.liakhovetski@xxxxxx> writes:
>
> > (moved to the new v4l list)
> >
> >> The DMA transfers in pxa_camera showed some weaknesses in
> >> multiple queued buffers context :
> >> - poll/select problem
> >> The order between list pcdev->capture and DMA chain was
> >> not the same. This creates a discrepancy between video
> >> buffers marked as "done" by the IRQ handler, and the
> >> really finished video buffer.
> >
> > Could you please describe where and how the order could get wrong?
Now after I've explained to you how the present DMA-chaining works, do you
still think the order can be swapped? If so, I need a new explanation:-)
> Sorry, I missed that point in the previous reply.
>
> It's still the same bit of code :
> - } else {
> - buf_dma->sg_cpu[nents].ddadr =
> - DDADR(pcdev->dma_chans[i]);
>
> That chains the end of the queued buffer to the active buffer
because, as we now know, this doesn't hold - we just use one (last) dummy
descriptor from the new buffer to append it to the current sg_tail, which
seems correct to me.
Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
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