Hi Maciej,
On Fri, May 6, 2022 at 4:44 PM Maciej W. Rozycki <macro@xxxxxxxxxxx> wrote:
On Fri, 6 May 2022, David Laight wrote:
It was retrofitted in that x86 systems already existed for ~15 years when
PCI came into picture. Therefore the makers of the CPU ISA couldn't have
envisaged the need for config access instructions like they did for memory
and port access.
Rev 2.0 of the PCI spec (1993) defines two mechanisms for config cycles.
#2 is probably the first one and maps all of PCI config space into
4k of IO space (PCI bridges aren't supported).
This one is even more horrid than #1 in that it requires two separate
preparatory I/O writes rather than just one, one to the Forward Register
(at 0xcfa) to set the bus number, and another to the Configuration Space
Enable Register (at 0xcf8) to set the function number, before you can
issue a configuration read or write to a device. So you need MP locking
too.
NB only peer bridges aren't supported with this mechanism, normal PCI-PCI
bridges are, via the Forward Register.
#1 requires a pair of accesses (and SMP locking).
Neither is really horrid.
Both are. First neither is MP-safe and second both are indirect in that
you need to poke at some chipset registers before you can issue the actual
read or write.
Sane access would require a single CPU instruction to read or write from
the configuration space. To access the conventional PCI configuration
space in a direct linear manner you need 256 * 21 * 8 * 256 = 10.5MiB of
address space. Such amount of address space seems affordable even with
32-bit systems.
Won't have fit in the legacy 1 MiB space ("640 KiB...").
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
