On Fri, 2022-05-06 at 13:27 +0100, Maciej W. Rozycki wrote:
On Fri, 6 May 2022, Arnd Bergmann wrote:
If this is PCI/PCIe indeed, then an I/O access is just a different bit
pattern put on the bus/in the TLP in the address phase. So what is there
inherent to the s390 architecture that prevents that different bit pattern
from being used?
The hardware design for PCI on s390 is very different from any other
architecture, and more abstract. Rather than implementing MMIO register
access as pointer dereference, this is a separate CPU instruction that
takes a device/bar plus offset as arguments rather than a pointer, and
Linux encodes this back into a fake __iomem token.
OK, that seems to me like a reasonable and quite a clean design (on the
hardware side).
So what happens if the instruction is given an I/O rather than memory BAR
as the relevant argument? Is the address space indicator bit (bit #0)
simply ignored or what?
See my answer to Arnd for some more background but there simply isn't a
way to formulate an I/O access. In the old style PCI instructions the
BAR number and the function handle are put in a register before the
access. BAR number 15 is used to access config space. If there is no
BAR for that number the instruction fails with a non-zero CC.
But that has nothing to do with the presence or absence of any specific
processor instructions. It's just a limitation of bus glue. So I guess
it's just that all PCI/PCIe glue logic implementations for s390 have such
a limitation, right?
There are separate instructions for PCI memory and config space, but
no instructions for I/O space, or for non-PCI MMIO that it could be mapped
into.
The PCI configuration space was retrofitted into x86 systems (and is
accessed in an awkward manner with them), but with a new design such a
clean approach is most welcome IMHO. Thank you for your explanation.
Maciej
Well our design is a retrofit too considering s390x is a direct
decendent of IBM System/360 which one could argue to have been the
first ISA. But yes as PCI support was only added with PCIe and with a
machine level hypervisor already in place we do get shielded a lot from
the gritty details.
