The __raw_read/__raw_write and read/write families of IO access functions
normally take address arguments of type "void __iomem *". The legacy
macros we are still using for ColdFire and non-MMU m68k don't really care,
they cast to volatile unsigned pointers of appropriate size to do their
work.
There is a lot of places in amongst the ColdFire and non-MMU m68k code
that we use direct constants as addresses with the read/write IO macros.
To convert to using the asm-generic/io.h version fo the __raw_ read/write
functions then we will need to be type clean. Otherwise we are going to
get _lots_ of warnings of the form:
In file included from ./arch/m68k/include/asm/mcfsim.h:24:0,
from arch/m68k/coldfire/intc-simr.c:20:
arch/m68k/coldfire/intc-simr.c: In function ‘init_IRQ’:
./arch/m68k/include/asm/m520xsim.h:40:29: warning: passing argument 2 of ‘__raw_writeb’ makes pointer from integer without a cast [-Wint-conversion]
#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
^
arch/m68k/coldfire/intc-simr.c:182:21: note: in expansion of macro ‘MCFINTC0_SIMR’
__raw_writeb(0xff, MCFINTC0_SIMR);
^
In file included from ./arch/m68k/include/asm/io_no.h:120:0,
from ./arch/m68k/include/asm/io.h:3,
from ./include/linux/io.h:25,
from ./include/linux/irq.h:25,
from ./include/asm-generic/hardirq.h:13,
from ./arch/m68k/include/asm/hardirq.h:25,
from ./include/linux/hardirq.h:9,
from ./include/linux/interrupt.h:13,
from arch/m68k/coldfire/intc-simr.c:16:
./include/asm-generic/io.h:71:22: note: expected ‘volatile void *’ but argument is of type ‘unsigned int’
#define __raw_writeb __raw_writeb
^
./include/asm-generic/io.h:72:20: note: in expansion of macro ‘__raw_writeb’
static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
^
Introduce a macro, iomem(), that converts a constant address to the
correct "void __iomem *" type.
Most conversions are simple and strait forward. A couple of cases in
pci.c required a little more work, since the address is also used as a
value to be read and written to a register.
Signed-off-by: Greg Ungerer <gerg@xxxxxxxxxxxxxx>
---
arch/m68k/coldfire/clk.c | 8 +++---
arch/m68k/coldfire/dma_timer.c | 20 +++++++--------
arch/m68k/coldfire/intc-2.c | 36 +++++++++++++--------------
arch/m68k/coldfire/intc-simr.c | 38 ++++++++++++++--------------
arch/m68k/coldfire/intc.c | 28 ++++++++++-----------
arch/m68k/coldfire/m520x.c | 26 +++++++++----------
arch/m68k/coldfire/m5272.c | 16 ++++++------
arch/m68k/coldfire/m528x.c | 29 +++++++++++-----------
arch/m68k/coldfire/m5441x.c | 8 +++---
arch/m68k/coldfire/m54xx.c | 20 ++++++++-------
arch/m68k/coldfire/pci.c | 55 +++++++++++++++++++++--------------------
arch/m68k/coldfire/pit.c | 2 +-
arch/m68k/coldfire/reset.c | 4 +--
arch/m68k/coldfire/sltimers.c | 4 +--
arch/m68k/coldfire/stmark2.c | 12 ++++-----
arch/m68k/coldfire/timers.c | 6 ++---
arch/m68k/include/asm/io_no.h | 6 +++++
arch/m68k/include/asm/mcfgpio.h | 12 ++++-----
18 files changed, 170 insertions(+), 160 deletions(-)
diff --git a/arch/m68k/coldfire/clk.c b/arch/m68k/coldfire/clk.c
index 849cd20..ceda70a 100644
--- a/arch/m68k/coldfire/clk.c
+++ b/arch/m68k/coldfire/clk.c
@@ -42,12 +42,12 @@ void __clk_init_disabled(struct clk *clk)
static void __clk_enable0(struct clk *clk)
{
- __raw_writeb(clk->slot, MCFPM_PPMCR0);
+ __raw_writeb(clk->slot, iomem(MCFPM_PPMCR0));
}
static void __clk_disable0(struct clk *clk)
{
- __raw_writeb(clk->slot, MCFPM_PPMSR0);
+ __raw_writeb(clk->slot, iomem(MCFPM_PPMSR0));
}
struct clk_ops clk_ops0 = {
@@ -58,12 +58,12 @@ struct clk_ops clk_ops0 = {
#ifdef MCFPM_PPMCR1
static void __clk_enable1(struct clk *clk)
{
- __raw_writeb(clk->slot, MCFPM_PPMCR1);
+ __raw_writeb(clk->slot, iomem(MCFPM_PPMCR1));
}
static void __clk_disable1(struct clk *clk)
{
- __raw_writeb(clk->slot, MCFPM_PPMSR1);
+ __raw_writeb(clk->slot, iomem(MCFPM_PPMSR1));
}
struct clk_ops clk_ops1 = {
diff --git a/arch/m68k/coldfire/dma_timer.c b/arch/m68k/coldfire/dma_timer.c
index cbb2894..afcde3d2 100644
--- a/arch/m68k/coldfire/dma_timer.c
+++ b/arch/m68k/coldfire/dma_timer.c
@@ -20,12 +20,12 @@
#define DMA_TIMER_2 (0x80)
#define DMA_TIMER_3 (0xc0)
-#define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400)
-#define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402)
-#define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403)
-#define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404)
-#define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408)
-#define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
+#define DTMR0 iomem(MCF_IPSBAR + DMA_TIMER_0 + 0x400)
+#define DTXMR0 iomem(MCF_IPSBAR + DMA_TIMER_0 + 0x402)
+#define DTER0 iomem(MCF_IPSBAR + DMA_TIMER_0 + 0x403)
+#define DTRR0 iomem(MCF_IPSBAR + DMA_TIMER_0 + 0x404)
+#define DTCR0 iomem(MCF_IPSBAR + DMA_TIMER_0 + 0x408)
+#define DTCN0 iomem(MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
#define DMA_FREQ ((MCF_CLK / 2) / 16)
@@ -56,10 +56,10 @@ static int __init init_cf_dt_clocksource(void)
* get a ~213 ns resolution and the 32bit register will overflow almost
* every 15 minutes.
*/
- __raw_writeb(0x00, DTXMR0);
- __raw_writeb(0x00, DTER0);
- __raw_writel(0x00000000, DTRR0);
- __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
+ __raw_writeb(0x00, iomem(DTXMR0));
+ __raw_writeb(0x00, iomem(DTER0));
+ __raw_writel(0x00000000, iomem(DTRR0));
+ __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, iomem(DTMR0));
return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
}
diff --git a/arch/m68k/coldfire/intc-2.c b/arch/m68k/coldfire/intc-2.c
index 9950933..4e3b8ad 100644
--- a/arch/m68k/coldfire/intc-2.c
+++ b/arch/m68k/coldfire/intc-2.c
@@ -50,13 +50,13 @@
static void intc_irq_mask(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
- unsigned long imraddr;
+ void __iomem *imraddr;
u32 val, imrbit;
#ifdef MCFICM_INTC1
- imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+ imraddr = iomem((irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0);
#else
- imraddr = MCFICM_INTC0;
+ imraddr = iomem(MCFICM_INTC0);
#endif
imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
imrbit = 0x1 << (irq & 0x1f);
@@ -68,13 +68,13 @@ static void intc_irq_mask(struct irq_data *d)
static void intc_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
- unsigned long imraddr;
+ void __iomem *imraddr;
u32 val, imrbit;
#ifdef MCFICM_INTC1
- imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+ imraddr = iomem((irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0);
#else
- imraddr = MCFICM_INTC0;
+ imraddr = iomem(MCFICM_INTC0);
#endif
imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
imrbit = 0x1 << (irq & 0x1f);
@@ -97,7 +97,7 @@ static void intc_irq_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
- __raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR);
+ __raw_writeb(0x1 << (irq - EINT0), iomem(MCFEPORT_EPFR));
}
/*
@@ -112,12 +112,12 @@ static void intc_irq_ack(struct irq_data *d)
static unsigned int intc_irq_startup(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
- unsigned long icraddr;
+ void __iomem *icraddr;
#ifdef MCFICM_INTC1
- icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+ icraddr = iomem((irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0);
#else
- icraddr = MCFICM_INTC0;
+ icraddr = iomem(MCFICM_INTC0);
#endif
icraddr += MCFINTC_ICR0 + (irq & 0x3f);
if (__raw_readb(icraddr) == 0)
@@ -130,12 +130,12 @@ static unsigned int intc_irq_startup(struct irq_data *d)
irq -= EINT0;
/* Set EPORT line as input */
- v = __raw_readb(MCFEPORT_EPDDR);
- __raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR);
+ v = __raw_readb(iomem(MCFEPORT_EPDDR));
+ __raw_writeb(v & ~(0x1 << irq), iomem(MCFEPORT_EPDDR));
/* Set EPORT line as interrupt source */
- v = __raw_readb(MCFEPORT_EPIER);
- __raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER);
+ v = __raw_readb(iomem(MCFEPORT_EPIER));
+ __raw_writeb(v | (0x1 << irq), iomem(MCFEPORT_EPIER));
}
intc_irq_unmask(d);
@@ -167,9 +167,9 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
irq_set_handler(irq, handle_edge_irq);
irq -= EINT0;
- pa = __raw_readw(MCFEPORT_EPPAR);
+ pa = __raw_readw(iomem(MCFEPORT_EPPAR));
pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2));
- __raw_writew(pa, MCFEPORT_EPPAR);
+ __raw_writew(pa, iomem(MCFEPORT_EPPAR));
return 0;
}
@@ -195,9 +195,9 @@ void __init init_IRQ(void)
int irq;
/* Mask all interrupt sources */
- __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
+ __raw_writel(0x1, iomem(MCFICM_INTC0 + MCFINTC_IMRL));
#ifdef MCFICM_INTC1
- __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
+ __raw_writel(0x1, iomem(MCFICM_INTC1 + MCFINTC_IMRL));
#endif
for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
diff --git a/arch/m68k/coldfire/intc-simr.c b/arch/m68k/coldfire/intc-simr.c
index 15c4b7a..ee5fa2a 100644
--- a/arch/m68k/coldfire/intc-simr.c
+++ b/arch/m68k/coldfire/intc-simr.c
@@ -69,11 +69,11 @@ static void intc_irq_mask(struct irq_data *d)
unsigned int irq = d->irq - MCFINT_VECBASE;
if (MCFINTC2_SIMR && (irq > 128))
- __raw_writeb(irq - 128, MCFINTC2_SIMR);
+ __raw_writeb(irq - 128, iomem(MCFINTC2_SIMR));
else if (MCFINTC1_SIMR && (irq > 64))
- __raw_writeb(irq - 64, MCFINTC1_SIMR);
+ __raw_writeb(irq - 64, iomem(MCFINTC1_SIMR));
else
- __raw_writeb(irq, MCFINTC0_SIMR);
+ __raw_writeb(irq, iomem(MCFINTC0_SIMR));
}
static void intc_irq_unmask(struct irq_data *d)
@@ -81,18 +81,18 @@ static void intc_irq_unmask(struct irq_data *d)
unsigned int irq = d->irq - MCFINT_VECBASE;
if (MCFINTC2_CIMR && (irq > 128))
- __raw_writeb(irq - 128, MCFINTC2_CIMR);
+ __raw_writeb(irq - 128, iomem(MCFINTC2_CIMR));
else if (MCFINTC1_CIMR && (irq > 64))
- __raw_writeb(irq - 64, MCFINTC1_CIMR);
+ __raw_writeb(irq - 64, iomem(MCFINTC1_CIMR));
else
- __raw_writeb(irq, MCFINTC0_CIMR);
+ __raw_writeb(irq, iomem(MCFINTC0_CIMR));
}
static void intc_irq_ack(struct irq_data *d)
{
unsigned int ebit = irq2ebit(d->irq);
- __raw_writeb(0x1 << ebit, MCFEPORT_EPFR);
+ __raw_writeb(0x1 << ebit, iomem(MCFEPORT_EPFR));
}
static unsigned int intc_irq_startup(struct irq_data *d)
@@ -105,22 +105,22 @@ static unsigned int intc_irq_startup(struct irq_data *d)
#if defined(MCFEPORT_EPDDR)
/* Set EPORT line as input */
- v = __raw_readb(MCFEPORT_EPDDR);
- __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
+ v = __raw_readb(iomem(MCFEPORT_EPDDR));
+ __raw_writeb(v & ~(0x1 << ebit), iomem(MCFEPORT_EPDDR));
#endif
/* Set EPORT line as interrupt source */
- v = __raw_readb(MCFEPORT_EPIER);
- __raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER);
+ v = __raw_readb(iomem(MCFEPORT_EPIER));
+ __raw_writeb(v | (0x1 << ebit), iomem(MCFEPORT_EPIER));
}
irq -= MCFINT_VECBASE;
if (MCFINTC2_ICR0 && (irq > 128))
- __raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
+ __raw_writeb(5, iomem(MCFINTC2_ICR0 + irq - 128));
else if (MCFINTC1_ICR0 && (irq > 64))
- __raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
+ __raw_writeb(5, iomem(MCFINTC1_ICR0 + irq - 64));
else
- __raw_writeb(5, MCFINTC0_ICR0 + irq);
+ __raw_writeb(5, iomem(MCFINTC0_ICR0 + irq));
intc_irq_unmask(d);
return 0;
@@ -151,9 +151,9 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
irq_set_handler(irq, handle_edge_irq);
ebit = irq2ebit(irq) * 2;
- pa = __raw_readw(MCFEPORT_EPPAR);
+ pa = __raw_readw(iomem(MCFEPORT_EPPAR));
pa = (pa & ~(0x3 << ebit)) | (tb << ebit);
- __raw_writew(pa, MCFEPORT_EPPAR);
+ __raw_writew(pa, iomem(MCFEPORT_EPPAR));
return 0;
}
@@ -179,11 +179,11 @@ void __init init_IRQ(void)
int irq, eirq;
/* Mask all interrupt sources */
- __raw_writeb(0xff, MCFINTC0_SIMR);
+ __raw_writeb(0xff, iomem(MCFINTC0_SIMR));
if (MCFINTC1_SIMR)
- __raw_writeb(0xff, MCFINTC1_SIMR);
+ __raw_writeb(0xff, iomem(MCFINTC1_SIMR));
if (MCFINTC2_SIMR)
- __raw_writeb(0xff, MCFINTC2_SIMR);
+ __raw_writeb(0xff, iomem(MCFINTC2_SIMR));
eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) +
(MCFINTC2_ICR0 ? 64 : 0);
diff --git a/arch/m68k/coldfire/intc.c b/arch/m68k/coldfire/intc.c
index cce2574..30b96da 100644
--- a/arch/m68k/coldfire/intc.c
+++ b/arch/m68k/coldfire/intc.c
@@ -45,23 +45,23 @@
void mcf_setimr(int index)
{
u16 imr;
- imr = __raw_readw(MCFSIM_IMR);
- __raw_writew(imr | (0x1 << index), MCFSIM_IMR);
+ imr = __raw_readw(iomem(MCFSIM_IMR));
+ __raw_writew(imr | (0x1 << index), iomem(MCFSIM_IMR));
}
void mcf_clrimr(int index)
{
u16 imr;
- imr = __raw_readw(MCFSIM_IMR);
- __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
+ imr = __raw_readw(iomem(MCFSIM_IMR));
+ __raw_writew(imr & ~(0x1 << index), iomem(MCFSIM_IMR));
}
void mcf_maskimr(unsigned int mask)
{
u16 imr;
- imr = __raw_readw(MCFSIM_IMR);
+ imr = __raw_readw(iomem(MCFSIM_IMR));
imr |= mask;
- __raw_writew(imr, MCFSIM_IMR);
+ __raw_writew(imr, iomem(MCFSIM_IMR));
}
#else
@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask)
void mcf_setimr(int index)
{
u32 imr;
- imr = __raw_readl(MCFSIM_IMR);
- __raw_writel(imr | (0x1 << index), MCFSIM_IMR);
+ imr = __raw_readl(iomem(MCFSIM_IMR));
+ __raw_writel(imr | (0x1 << index), iomem(MCFSIM_IMR));
}
void mcf_clrimr(int index)
{
u32 imr;
- imr = __raw_readl(MCFSIM_IMR);
- __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
+ imr = __raw_readl(iomem(MCFSIM_IMR));
+ __raw_writel(imr & ~(0x1 << index), iomem(MCFSIM_IMR));
}
void mcf_maskimr(unsigned int mask)
{
u32 imr;
- imr = __raw_readl(MCFSIM_IMR);
+ imr = __raw_readl(iomem(MCFSIM_IMR));
imr |= mask;
- __raw_writel(imr, MCFSIM_IMR);
+ __raw_writel(imr, iomem(MCFSIM_IMR));
}
#endif
@@ -104,9 +104,9 @@ void mcf_autovector(int irq)
#ifdef MCFSIM_AVR
if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
u8 avec;
- avec = __raw_readb(MCFSIM_AVR);
+ avec = __raw_readb(iomem(MCFSIM_AVR));
avec |= (0x1 << (irq - EIRQ1 + 1));
- __raw_writeb(avec, MCFSIM_AVR);
+ __raw_writeb(avec, iomem(MCFSIM_AVR));
}
#endif
}
diff --git a/arch/m68k/coldfire/m520x.c b/arch/m68k/coldfire/m520x.c
index b5b2a26..26b4f86 100644
--- a/arch/m68k/coldfire/m520x.c
+++ b/arch/m68k/coldfire/m520x.c
@@ -124,11 +124,11 @@ static void __init m520x_qspi_init(void)
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
u16 par;
/* setup Port QS for QSPI with gpio CS control */
- writeb(0x3f, MCF_GPIO_PAR_QSPI);
+ writeb(0x3f, iomem(MCF_GPIO_PAR_QSPI));
/* make U1CTS and U2RTS gpio for cs_control */
- par = readw(MCF_GPIO_PAR_UART);
+ par = readw(iomem(MCF_GPIO_PAR_UART));
par &= 0x00ff;
- writew(par, MCF_GPIO_PAR_UART);
+ writew(par, iomem(MCF_GPIO_PAR_UART));
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
@@ -141,9 +141,9 @@ static void __init m520x_i2c_init(void)
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
- par = readb(MCF_GPIO_PAR_FECI2C);
+ par = readb(iomem(MCF_GPIO_PAR_FECI2C));
par |= 0x0f;
- writeb(par, MCF_GPIO_PAR_FECI2C);
+ writeb(par, iomem(MCF_GPIO_PAR_FECI2C));
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
@@ -155,17 +155,17 @@ static void __init m520x_uarts_init(void)
u8 par2;
/* UART0 and UART1 GPIO pin setup */
- par = readw(MCF_GPIO_PAR_UART);
+ par = readw(iomem(MCF_GPIO_PAR_UART));
par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
- writew(par, MCF_GPIO_PAR_UART);
+ writew(par, iomem(MCF_GPIO_PAR_UART));
/* UART1 GPIO pin setup */
- par2 = readb(MCF_GPIO_PAR_FECI2C);
+ par2 = readb(iomem(MCF_GPIO_PAR_FECI2C));
par2 &= ~0x0F;
par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
- writeb(par2, MCF_GPIO_PAR_FECI2C);
+ writeb(par2, iomem(MCF_GPIO_PAR_FECI2C));
}
/***************************************************************************/
@@ -175,11 +175,11 @@ static void __init m520x_fec_init(void)
u8 v;
/* Set multi-function pins to ethernet mode */
- v = readb(MCF_GPIO_PAR_FEC);
- writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
+ v = readb(iomem(MCF_GPIO_PAR_FEC));
+ writeb(v | 0xf0, iomem(MCF_GPIO_PAR_FEC));
- v = readb(MCF_GPIO_PAR_FECI2C);
- writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
+ v = readb(iomem(MCF_GPIO_PAR_FECI2C));
+ writeb(v | 0x0f, iomem(MCF_GPIO_PAR_FECI2C));
}
/***************************************************************************/
diff --git a/arch/m68k/coldfire/m5272.c b/arch/m68k/coldfire/m5272.c
index ad1185c..7577132 100644
--- a/arch/m68k/coldfire/m5272.c
+++ b/arch/m68k/coldfire/m5272.c
@@ -64,13 +64,13 @@ static void __init m5272_uarts_init(void)
u32 v;
/* Enable the output lines for the serial ports */
- v = readl(MCFSIM_PBCNT);
+ v = readl(iomem(MCFSIM_PBCNT));
v = (v & ~0x000000ff) | 0x00000055;
- writel(v, MCFSIM_PBCNT);
+ writel(v, iomem(MCFSIM_PBCNT));
- v = readl(MCFSIM_PDCNT);
+ v = readl(iomem(MCFSIM_PDCNT));
v = (v & ~0x000003fc) | 0x000002a8;
- writel(v, MCFSIM_PDCNT);
+ writel(v, iomem(MCFSIM_PDCNT));
}
/***************************************************************************/
@@ -79,9 +79,9 @@ static void m5272_cpu_reset(void)
{
local_irq_disable();
/* Set watchdog to reset, and enabled */
- __raw_writew(0, MCFSIM_WIRR);
- __raw_writew(1, MCFSIM_WRRR);
- __raw_writew(0, MCFSIM_WCR);
+ __raw_writew(0, iomem(MCFSIM_WIRR));
+ __raw_writew(1, iomem(MCFSIM_WRRR));
+ __raw_writew(0, iomem(MCFSIM_WCR));
for (;;)
/* wait for watchdog to timeout */;
}
@@ -92,7 +92,7 @@ void __init config_BSP(char *commandp, int size)
{
#if defined (CONFIG_MOD5272)
/* Set base of device vectors to be 64 */
- writeb(0x40, MCFSIM_PIVR);
+ writeb(0x40, iomem(MCFSIM_PIVR));
#endif
#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
diff --git a/arch/m68k/coldfire/m528x.c b/arch/m68k/coldfire/m528x.c
index 7ad3193..6ecb025 100644
--- a/arch/m68k/coldfire/m528x.c
+++ b/arch/m68k/coldfire/m528x.c
@@ -61,7 +61,7 @@ static void __init m528x_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/* setup Port QS for QSPI with gpio CS control */
- __raw_writeb(0x07, MCFGPIO_PQSPAR);
+ __raw_writeb(0x07, iomem(MCFGPIO_PQSPAR));
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
@@ -74,9 +74,9 @@ static void __init m528x_i2c_init(void)
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
- paspar = readw(MCFGPIO_PASPAR);
+ paspar = readw(iomem(MCFGPIO_PASPAR));
paspar |= 0xF;
- writew(paspar, MCFGPIO_PASPAR);
+ writew(paspar, iomem(MCFGPIO_PASPAR));
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
@@ -87,9 +87,9 @@ static void __init m528x_uarts_init(void)
u8 port;
/* make sure PUAPAR is set for UART0 and UART1 */
- port = readb(MCFGPIO_PUAPAR);
+ port = readb(iomem(MCFGPIO_PUAPAR));
port |= 0x03 | (0x03 << 2);
- writeb(port, MCFGPIO_PUAPAR);
+ writeb(port, iomem(MCFGPIO_PUAPAR));
}
/***************************************************************************/
@@ -99,9 +99,9 @@ static void __init m528x_fec_init(void)
u16 v16;
/* Set multi-function pins to ethernet mode for fec0 */
- v16 = readw(MCFGPIO_PASPAR);
- writew(v16 | 0xf00, MCFGPIO_PASPAR);
- writeb(0xc0, MCFGPIO_PEHLPAR);
+ v16 = readw(iomem(MCFGPIO_PASPAR));
+ writew(v16 | 0xf00, iomem(MCFGPIO_PASPAR));
+ writeb(0xc0, iomem(MCFGPIO_PEHLPAR));
}
/***************************************************************************/
@@ -109,8 +109,8 @@ static void __init m528x_fec_init(void)
#ifdef CONFIG_WILDFIRE
void wildfire_halt(void)
{
- writeb(0, 0x30000007);
- writeb(0x2, 0x30000007);
+ writeb(0, iomem(0x30000007));
+ writeb(0x2, iomem(0x30000007));
}
#endif
@@ -120,14 +120,15 @@ void wildfiremod_halt(void)
printk(KERN_INFO "WildFireMod hibernating...\n");
/* Set portE.5 to Digital IO */
- writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR);
+ writew(readw(iomem(MCFGPIO_PEPAR)) & ~(1 << (5 * 2)),
+ iomem(MCFGPIO_PEPAR));
/* Make portE.5 an output */
- writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
+ writeb(readb(iomem(MCFGPIO_PDDR_E)) | (1 << 5), iomem(MCFGPIO_PDDR_E));
/* Now toggle portE.5 from low to high */
- writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
- writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
+ writeb(readb(iomem(MCFGPIO_PODR_E)) & ~(1 << 5), iomem(MCFGPIO_PODR_E));
+ writeb(readb(iomem(MCFGPIO_PODR_E)) | (1 << 5), iomem(MCFGPIO_PODR_E));
printk(KERN_EMERG "Failed to hibernate. Halting!\n");
}
diff --git a/arch/m68k/coldfire/m5441x.c b/arch/m68k/coldfire/m5441x.c
index 55392af..53b8ebb 100644
--- a/arch/m68k/coldfire/m5441x.c
+++ b/arch/m68k/coldfire/m5441x.c
@@ -207,14 +207,14 @@ static void __init m5441x_clk_init(void)
static void __init m5441x_uarts_init(void)
{
- __raw_writeb(0x0f, MCFGPIO_PAR_UART0);
- __raw_writeb(0x00, MCFGPIO_PAR_UART1);
- __raw_writeb(0x00, MCFGPIO_PAR_UART2);
+ __raw_writeb(0x0f, iomem(MCFGPIO_PAR_UART0));
+ __raw_writeb(0x00, iomem(MCFGPIO_PAR_UART1));
+ __raw_writeb(0x00, iomem(MCFGPIO_PAR_UART2));
}
static void __init m5441x_fec_init(void)
{
- __raw_writeb(0x03, MCFGPIO_PAR_FEC);
+ __raw_writeb(0x03, iomem(MCFGPIO_PAR_FEC));
}
void __init config_BSP(char *commandp, int size)
diff --git a/arch/m68k/coldfire/m54xx.c b/arch/m68k/coldfire/m54xx.c
index adad03c..6597e46 100644
--- a/arch/m68k/coldfire/m54xx.c
+++ b/arch/m68k/coldfire/m54xx.c
@@ -58,12 +58,14 @@ struct clk *mcf_clks[] = {
static void __init m54xx_uarts_init(void)
{
/* enable io pins */
- __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
+ __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
+ iomem(MCFGPIO_PAR_PSC0));
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
- MCFGPIO_PAR_PSC1);
+ iomem(MCFGPIO_PAR_PSC1));
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
- MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
- __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
+ MCF_PAR_PSC_CTS_CTS, iomem(MCFGPIO_PAR_PSC2));
+ __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
+ iomem(MCFGPIO_PAR_PSC3));
}
/***************************************************************************/
@@ -74,9 +76,9 @@ static void __init m54xx_i2c_init(void)
u32 r;
/* set the fec/i2c/irq pin assignment register for i2c */
- r = readl(MCF_PAR_FECI2CIRQ);
+ r = readl(iomem(MCF_PAR_FECI2CIRQ));
r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
- writel(r, MCF_PAR_FECI2CIRQ);
+ writel(r, iomem(MCF_PAR_FECI2CIRQ));
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
@@ -86,10 +88,10 @@ static void mcf54xx_reset(void)
{
/* disable interrupts and enable the watchdog */
asm("movew #0x2700, %sr\n");
- __raw_writel(0, MCF_GPT_GMS0);
- __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
+ __raw_writel(0, iomem(MCF_GPT_GMS0));
+ __raw_writel(MCF_GPT_GCIR_CNT(1), iomem(MCF_GPT_GCIR0));
__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
- MCF_GPT_GMS0);
+ iomem(MCF_GPT_GMS0));
}
/***************************************************************************/
diff --git a/arch/m68k/coldfire/pci.c b/arch/m68k/coldfire/pci.c
index db709ad..dc6d125 100644
--- a/arch/m68k/coldfire/pci.c
+++ b/arch/m68k/coldfire/pci.c
@@ -28,7 +28,7 @@
* the IO map space when we enable it in the PCICAR register.
*/
static struct pci_bus *rootbus;
-static unsigned long iospace;
+static void __iomem *iospace;
/*
* We need to be carefull probing on bus 0 (directly connected to host
@@ -65,7 +65,8 @@ static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)
static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *value)
{
- unsigned long addr;
+ unsigned long offset;
+ void __iomem *addr;
*value = 0xffffffff;
@@ -75,8 +76,8 @@ static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
}
syncio();
- addr = mcf_mk_pcicar(bus->number, devfn, where);
- __raw_writel(PCICAR_E | addr, PCICAR);
+ offset = mcf_mk_pcicar(bus->number, devfn, where);
+ __raw_writel(PCICAR_E | offset, iomem(PCICAR));
addr = iospace + (where & 0x3);
switch (size) {
@@ -92,14 +93,15 @@ static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
}
syncio();
- __raw_writel(0, PCICAR);
+ __raw_writel(0, iomem(PCICAR));
return PCIBIOS_SUCCESSFUL;
}
static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 value)
{
- unsigned long addr;
+ unsigned long offset;
+ void __iomem *addr;
if (bus->number == 0) {
if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
@@ -107,8 +109,8 @@ static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
}
syncio();
- addr = mcf_mk_pcicar(bus->number, devfn, where);
- __raw_writel(PCICAR_E | addr, PCICAR);
+ offset = mcf_mk_pcicar(bus->number, devfn, where);
+ __raw_writel(PCICAR_E | offset, iomem(PCICAR));
addr = iospace + (where & 0x3);
switch (size) {
@@ -124,7 +126,7 @@ static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
}
syncio();
- __raw_writel(0, PCICAR);
+ __raw_writel(0, iomem(PCICAR));
return PCIBIOS_SUCCESSFUL;
}
@@ -182,25 +184,25 @@ static int __init mcf_pci_init(void)
pr_info("ColdFire: PCI bus initialization...\n");
/* Reset the external PCI bus */
- __raw_writel(PCIGSCR_RESET, PCIGSCR);
- __raw_writel(0, PCITCR);
+ __raw_writel(PCIGSCR_RESET, iomem(PCIGSCR));
+ __raw_writel(0, iomem(PCITCR));
request_resource(&iomem_resource, &mcf_pci_mem);
request_resource(&iomem_resource, &mcf_pci_io);
/* Configure PCI arbiter */
__raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
- PACR_EXTMINTE(0x1f), PACR);
+ PACR_EXTMINTE(0x1f), iomem(PACR));
/* Set required multi-function pins for PCI bus use */
- __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
- __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
+ __raw_writew(0x3ff, iomem(MCFGPIO_PAR_PCIBG));
+ __raw_writew(0x3ff, iomem(MCFGPIO_PAR_PCIBR));
/* Set up config space for local host bus controller */
__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
- PCI_COMMAND_INVALIDATE, PCISCR);
- __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
- __raw_writel(0, PCICR2);
+ PCI_COMMAND_INVALIDATE, iomem(PCISCR));
+ __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), iomem(PCICR1));
+ __raw_writel(0, iomem(PCICR2));
/*
* Set up the initiator windows for memory and IO mapping.
@@ -208,28 +210,27 @@ static int __init mcf_pci_init(void)
* PCI memory and IO address spaces.
*/
__raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
- PCIIW0BTAR);
+ iomem(PCIIW0BTAR));
__raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
- PCIIW1BTAR);
+ iomem(PCIIW1BTAR));
__raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
- PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
+ PCIIWCR_W1_IO | PCIIWCR_W1_E, iomem(PCIIWCR));
/*
* Set up the target windows for access from the PCI bus back to the
* CPU bus. All we need is access to system RAM (for mastering).
*/
- __raw_writel(CONFIG_RAMBASE, PCIBAR1);
- __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
+ __raw_writel(CONFIG_RAMBASE, iomem(PCIBAR1));
+ __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, iomem(PCITBATR1));
/* Keep a virtual mapping to IO/config space active */
- iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
- if (iospace == 0)
+ iospace = ioremap(PCI_IO_PA, PCI_IO_SIZE);
+ if (IS_ERR(iospace))
return -ENODEV;
- pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
- (u32) iospace);
+ pr_info("Coldfire: PCI IO/config window mapped to 0x%p\n", iospace);
/* Turn of PCI reset, and wait for devices to settle */
- __raw_writel(0, PCIGSCR);
+ __raw_writel(0, iomem(PCIGSCR));
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(msecs_to_jiffies(200));
diff --git a/arch/m68k/coldfire/pit.c b/arch/m68k/coldfire/pit.c
index eb6f16b..c26359b 100644
--- a/arch/m68k/coldfire/pit.c
+++ b/arch/m68k/coldfire/pit.c
@@ -32,7 +32,7 @@
* By default use timer1 as the system clock timer.
*/
#define FREQ ((MCF_CLK / 2) / 64)
-#define TA(a) (MCFPIT_BASE1 + (a))
+#define TA(a) iomem(MCFPIT_BASE1 + (a))
#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
static u32 pit_cnt;
diff --git a/arch/m68k/coldfire/reset.c b/arch/m68k/coldfire/reset.c
index f30952f..1acfc70 100644
--- a/arch/m68k/coldfire/reset.c
+++ b/arch/m68k/coldfire/reset.c
@@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
{
local_irq_disable();
/* Set watchdog to soft reset, and enabled */
- __raw_writeb(0xc0, MCFSIM_SYPCR);
+ __raw_writeb(0xc0, iomem(MCFSIM_SYPCR));
for (;;)
/* wait for watchdog to timeout */;
}
@@ -37,7 +37,7 @@ static void mcf_cpu_reset(void)
static void mcf_cpu_reset(void)
{
local_irq_disable();
- __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
+ __raw_writeb(MCF_RCR_SWRESET, iomem(MCF_RCR));
}
#endif
diff --git a/arch/m68k/coldfire/sltimers.c b/arch/m68k/coldfire/sltimers.c
index 1b11e7b..1cde8ae 100644
--- a/arch/m68k/coldfire/sltimers.c
+++ b/arch/m68k/coldfire/sltimers.c
@@ -33,7 +33,7 @@
/*
* By default use Slice Timer 1 as the profiler clock timer.
*/
-#define PA(a) (MCFSLT_TIMER1 + (a))
+#define PA(a) iomem(MCFSLT_TIMER1 + (a))
/*
* Choose a reasonably fast profile timer. Make it an odd value to
@@ -77,7 +77,7 @@ void mcfslt_profile_init(void)
/*
* By default use Slice Timer 0 as the system clock timer.
*/
-#define TA(a) (MCFSLT_TIMER0 + (a))
+#define TA(a) iomem(MCFSLT_TIMER0 + (a))
static u32 mcfslt_cycles_per_jiffy;
static u32 mcfslt_cnt;
diff --git a/arch/m68k/coldfire/stmark2.c b/arch/m68k/coldfire/stmark2.c
index a8d2b3d..59be925 100644
--- a/arch/m68k/coldfire/stmark2.c
+++ b/arch/m68k/coldfire/stmark2.c
@@ -99,14 +99,14 @@
static int __init init_stmark2(void)
{
/* DSPI0, all pins as DSPI, and using CS1 */
- __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL);
- __raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH);
+ __raw_writeb(0x80, iomem(MCFGPIO_PAR_DSPIOWL));
+ __raw_writeb(0xfc, iomem(MCFGPIO_PAR_DSPIOWH));
/* Board gpio setup */
- __raw_writeb(0x00, MCFGPIO_PAR_BE);
- __raw_writeb(0x00, MCFGPIO_PAR_FBCTL);
- __raw_writeb(0x00, MCFGPIO_PAR_CS);
- __raw_writeb(0x00, MCFGPIO_PAR_CANI2C);
+ __raw_writeb(0x00, iomem(MCFGPIO_PAR_BE));
+ __raw_writeb(0x00, iomem(MCFGPIO_PAR_FBCTL));
+ __raw_writeb(0x00, iomem(MCFGPIO_PAR_CS));
+ __raw_writeb(0x00, iomem(MCFGPIO_PAR_CANI2C));
platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices));
diff --git a/arch/m68k/coldfire/timers.c b/arch/m68k/coldfire/timers.c
index 227aa5d..a3139c8 100644
--- a/arch/m68k/coldfire/timers.c
+++ b/arch/m68k/coldfire/timers.c
@@ -29,7 +29,7 @@
* By default use timer1 as the system clock timer.
*/
#define FREQ (MCF_BUSCLK / 16)
-#define TA(a) (MCFTIMER_BASE1 + (a))
+#define TA(a) iomem(MCFTIMER_BASE1 + (a))
/*
* These provide the underlying interrupt vector support.
@@ -57,13 +57,13 @@ static void init_timer_irq(void)
#ifdef MCFSIM_ICR_AUTOVEC
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
- MCFSIM_TIMER1ICR);
+ iomem(MCFSIM_TIMER1ICR));
mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
- MCFSIM_TIMER2ICR);
+ iomem(MCFSIM_TIMER2ICR));
mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
#endif
#endif /* MCFSIM_ICR_AUTOVEC */
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
index 4fe743f..95e70b5 100644
--- a/arch/m68k/include/asm/io_no.h
+++ b/arch/m68k/include/asm/io_no.h
@@ -3,6 +3,12 @@
#define _M68KNOMMU_IO_H
/*
+ * Convert a physical memory address into a IO memory address.
+ * For us this is trivially a type cast.
+ */
+#define iomem(a) ((void __iomem *) (a))
+
+/*
* The non-MMU m68k and ColdFire IO and memory mapped hardware accesses
* functions have always worked in CPU native endian. We need to define
* that behavior here first before we include asm-generic/io.h.
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index 66203c3..4b5409d 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -111,8 +111,8 @@ static inline void gpio_free(unsigned gpio)
#define MCFGPIO_PORTTYPE u8
#define MCFGPIO_PORTSIZE 8
-#define mcfgpio_read(port) __raw_readb(port)
-#define mcfgpio_write(data, port) __raw_writeb(data, port)
+#define mcfgpio_read(port) __raw_readb(iomem(port))
+#define mcfgpio_write(data, port) __raw_writeb(data, iomem(port))
#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
@@ -120,8 +120,8 @@ static inline void gpio_free(unsigned gpio)
#define MCFGPIO_PORTTYPE u16
#define MCFGPIO_PORTSIZE 16
-#define mcfgpio_read(port) __raw_readw(port)
-#define mcfgpio_write(data, port) __raw_writew(data, port)
+#define mcfgpio_read(port) __raw_readw(iomem(port))
+#define mcfgpio_write(data, port) __raw_writew(data, iomem(port))
#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
@@ -129,8 +129,8 @@ static inline void gpio_free(unsigned gpio)
#define MCFGPIO_PORTTYPE u32
#define MCFGPIO_PORTSIZE 32
-#define mcfgpio_read(port) __raw_readl(port)
-#define mcfgpio_write(data, port) __raw_writel(data, port)
+#define mcfgpio_read(port) __raw_readl(iomem(port))
+#define mcfgpio_write(data, port) __raw_writel(data, iomem(port))
#endif
--
1.9.1
--
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