On Mon, 26 May 2014, Geert Uytterhoeven wrote:
On Mon, May 26, 2014 at 10:56 AM, Michael Schmitz <schmitzmic@xxxxxxxxx>
wrote:
+ /* Wait for 5 PCLK cycles, which is about 63 CPU cycles */
+ /* 5 / 7.9872 MHz = approx. 0.63 us = 63 / 100 MHz */
The original Falcon and TT had a 16 MHz CPU clock IIRC.
This loop is meant to introduce a minimum delay, right? So assuming a
100 MHz CPU will only prolong the delay on slower CPUs, which is safe.
Right. It's intended to cope with CPU upgrades.
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