Hi,
the way I understood post-increment to work was for this to happen
only after instruction execution. If the effective address had been
modified already, it would be more difficult for an emulator to
determine the correct address after the trap. Also, it seems more
efficient to first decode the instruction (and trap if needed) before
fully decoding the address.
Michael (posting from gmail since my old mail account has gone down
in flames with a RAID5 crash at my old lab ...)
On Fri, Jul 23, 2010 at 8:39 PM, Mattias Engdegård
<mattiase@xxxxxxxxxxxx> wrote:
23 jul 2010 kl. 06.12 skrev Finn Thain:
I ran this on a PowerBook 190cs:
postinc: result -3.500000 (expected -3.500000), address 0xef8ddcf8
(expected 0xef8ddcf8)
predec: result 1.750000 (expected 1.750000), address 0xef8ddcf0 (expected
0xef8ddcf0)
Thank you! It indicates that the address generation does not alter any
registers (because the FPU emulation will do so, and we didn't see a
duplicated change). This is a bit surprising to me, but your evidence cannot
be refuted. Anyway, it's good to have cast light on the matter.
(And Geert can say "told you so".)
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