All,
Reply again to plain text format & line-warp and trim agree part as Jones's suggestion,
please let me know if there are still having format issue.
please kindly to check our comments with ">>" beginning.
-----Original Message-----
From: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Sent: Tuesday, November 14, 2023 10:19 PM
To: larry.lai <larry.lai@xxxxxxxxxxxxxxx>
Cc: lee@xxxxxxxxxx; linus.walleij@xxxxxxxxxx; pavel@xxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-gpio@xxxxxxxxxxxxxxx; linux-leds@xxxxxxxxxxxxxxx; GaryWang 汪之逸 <GaryWang@xxxxxxxxxxxx>; musa.lin@xxxxxxxxxxxxxxx; jack.chang@xxxxxxxxxxxxxxx; noah.hung@xxxxxxxxxxxxxxx
Subject: Re: [PATCH V7 2/3] pinctrl: Add support pin control for UP board CPLD/FPGA
On Tue, Oct 31, 2023 at 09:51:18AM +0800, larry.lai wrote:
> The UP Squared board
> <http://www.upboard.com/> implements certain features (pin control) through an on-board FPGA.
>
> Reported-by: kernel test robot <lkp@xxxxxxxxx>
> Signed-off-by: Gary Wang <garywang@xxxxxxxxxxxx>
> Signed-off-by: larry.lai <larry.lai@xxxxxxxxxxxxxxx>
> +#include "intel/pinctrl-intel.h"
I do not think it's correct use of the header.
>> see below
...
> +/* Offset from regs */
> +#define REVID 0x000
> +#define REVID_SHIFT 16
> +#define REVID_MASK GENMASK(31, 16)
> +#define PADBAR 0x00c
> +
> +/* Offset from pad_regs */
> +#define PADCFG0 0x000
> +#define PADCFG0_RXEVCFG_SHIFT 25
> +#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
> +#define PADCFG0_RXEVCFG_LEVEL 0
> +#define PADCFG0_RXEVCFG_EDGE 1
> +#define PADCFG0_RXEVCFG_DISABLED 2
> +#define PADCFG0_RXEVCFG_EDGE_BOTH 3
> +#define PADCFG0_PREGFRXSEL BIT(24)
> +#define PADCFG0_RXINV BIT(23)
> +#define PADCFG0_GPIROUTIOXAPIC BIT(20)
> +#define PADCFG0_GPIROUTSCI BIT(19)
> +#define PADCFG0_GPIROUTSMI BIT(18)
> +#define PADCFG0_GPIROUTNMI BIT(17)
> +#define PADCFG0_PMODE_SHIFT 10
> +#define PADCFG0_PMODE_MASK GENMASK(13, 10)
> +#define PADCFG0_PMODE_GPIO 0
> +#define PADCFG0_GPIORXDIS BIT(9)
> +#define PADCFG0_GPIOTXDIS BIT(8)
> +#define PADCFG0_GPIORXSTATE BIT(1)
> +#define PADCFG0_GPIOTXSTATE BIT(0)
> +
> +#define PADCFG1 0x004
> +#define PADCFG1_TERM_UP BIT(13)
> +#define PADCFG1_TERM_SHIFT 10
> +#define PADCFG1_TERM_MASK GENMASK(12, 10)
> +#define PADCFG1_TERM_20K BIT(2)
> +#define PADCFG1_TERM_5K BIT(1)
> +#define PADCFG1_TERM_1K BIT(0)
> +#define PADCFG1_TERM_833 (BIT(1) | BIT(0))
> +
> +#define PADCFG2 0x008
> +#define PADCFG2_DEBEN BIT(0)
> +#define PADCFG2_DEBOUNCE_SHIFT 1
> +#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
> +
> +#define DEBOUNCE_PERIOD_NSEC 31250
> +
> +/* Additional features supported by the hardware */
> +#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
> +#define PINCTRL_FEATURE_1K_PD BIT(1)
Huh?! No way it should be here in _any_ form!
>> actually we need set pad mode at runtime for HAP pins GPIO, could considering let pinctrl-upboard using it??
it's not a good way but get register offset from intel_pinctrl structure can reduce 28~48 pin offset data for each board.
...
With Best Regards,
Andy Shevchenko
