On Tue, 26 Sept 2023 at 14:27, Masahiro Yamada <masahiroy@xxxxxxxxxx> wrote:
>
> On Tue, Sep 26, 2023 at 8:37 PM Ard Biesheuvel <ardb@xxxxxxxxxx> wrote:
> >
> > Hello Masahiro,
> >
> > Thanks for getting to the bottom of this.
> >
> > The patch looks correct to me, but could we please drop this huge
> > commit log text? The AAPCS simply states that a BL instruction might
> > clobber IP, so any inline asm that contains a BL should have IP in its
> > clobber list. In our case, the use of PIC veneers is what might cause
> > this, so we should mention that as well. But your entire journey to
> > get to that conclusion is not something that deserves to be included
> > in the git commit log forever, imho.
> >
> > So with the commit log trimmed:
> >
> > Reviewed-by: Ard Biesheuvel <ardb@xxxxxxxxxx>
>
>
>
> Is this commit log OK?
>
Yes, thanks for rewriting it.
I don't think a resend is necessary - please drop this in Russell's
patch tracker.
Thanks,
>
> ===================================>8============================
> The 32-bit ARM kernel stops working if the kernel grows to the point
> where veneers for __get_user_* are created.
>
> AAPCS32 [1] states, "Register r12 (IP) may be used by a linker as a
> scratch register between a routine and any subroutine it calls. It
> can also be used within a routine to hold intermediate values between
> subroutine calls."
>
> However, the bl instruction buried within the inline asm is unpredictable
> for compilers; hence, "ip" must be added to the clobber list.
>
> This becomes critical when veneers for __get_user_* are created because
> veneers use the ip register since commit 02e541db0540 ("ARM: 8323/1:
> force linker to use PIC veneers").
>
> [1]: https://github.com/ARM-software/abi-aa/blob/2023Q1/aapcs32/aapcs32.rst
> ===================================>8============================
>
>
>
>
>
>
> --
> Best Regards
> Masahiro Yamada
