On Fri, Oct 09, 2009 at 08:45:09AM +0530, kartikeyan sadasivuni wrote:
> hi,
>
> I have a kernel module Makefile requirement as follows (unavoidable)
> prefix-foo.o should be generated by foo.c using Kbuild
> Right now I am doing the following
> =====
> $(obj-m:%.o=%)-objs += $(MORE_OBJS:%=prefix-%)
> $(obj)/prefix-%.o : $(src)/%.c # prefix-foo.o from foo.c
> $(CC) $(c_flags) -c -o $@ $< #line3
> =====
> Is there is a better kernel builtin way to write line-3
> without module Makefile having quiet_cmd_* and cmd_* stuff,
> some thing like
> $(obj)/prefix-%.o : $(src)/%.c
> $(call cmd,prefix-$@) #without quiet_cmd_*,cmd_* in module Makefile
>
> kartikeyan
Is it an option for you to create a copy of said file?
Something like this (untested).
$(obj)/prefix-foo.c: $(src)/foo.c
cat $< > $@ || (rm $@ && flase)
obj-m += prefix.o
Notes: Use cat rather than copy to avoid potential umask related issues.
(rm $@ && false) delte the file if something went
wrong and we only piped half the file.
Sam
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