hi, I have a kernel module Makefile requirement as follows (unavoidable) prefix-foo.o should be generated by foo.c using Kbuild Right now I am doing the following ===== $(obj-m:%.o=%)-objs += $(MORE_OBJS:%=prefix-%) $(obj)/prefix-%.o : $(src)/%.c # prefix-foo.o from foo.c $(CC) $(c_flags) -c -o $@ $< #line3 ===== Is there is a better kernel builtin way to write line-3 without module Makefile having quiet_cmd_* and cmd_* stuff, some thing like $(obj)/prefix-%.o : $(src)/%.c $(call cmd,prefix-$@) #without quiet_cmd_*,cmd_* in module Makefile kartikeyan -- S.Kartikeyan -- To unsubscribe from this list: send the line "unsubscribe linux-kbuild" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
