>-----Original Message----- >From: Zhang, Lixu >Sent: Thursday, May 30, 2024 3:42 PM >To: srinivas pandruvada <srinivas.pandruvada@xxxxxxxxxxxxxxx>; Arnd >Bergmann <arnd@xxxxxxxx>; Arnd Bergmann <arnd@xxxxxxxxxx>; Jiri Kosina ><jikos@xxxxxxxxxx>; Benjamin Tissoires <bentiss@xxxxxxxxxx>; Xu, Even ><even.xu@xxxxxxxxx> >Cc: linux-input@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx >Subject: RE: [PATCH 1/2] HID: intel-ish-hid: fix cache management mistake > >>-----Original Message----- >>From: srinivas pandruvada <srinivas.pandruvada@xxxxxxxxxxxxxxx> >>Sent: Thursday, May 30, 2024 6:25 AM >>To: Arnd Bergmann <arnd@xxxxxxxx>; Zhang, Lixu <lixu.zhang@xxxxxxxxx>; >>Arnd Bergmann <arnd@xxxxxxxxxx>; Jiri Kosina <jikos@xxxxxxxxxx>; >>Benjamin Tissoires <bentiss@xxxxxxxxxx> >>Cc: linux-input@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx >>Subject: Re: [PATCH 1/2] HID: intel-ish-hid: fix cache management >>mistake >> >>On Wed, 2024-05-29 at 09:06 +0200, Arnd Bergmann wrote: >>> On Wed, May 29, 2024, at 08:46, Zhang, Lixu wrote: >>> > > >>> > >>> > > + dma_wmb(); >>> > I tested it on the platform, but it didn't wok. >>> > >>> >>> What behavior do you see instead? >Hi Arnd, please refer to the information below. > >>> If the manual cache flush works >>> around a bug, that would indicate that the device itself is not >>> coherent and the dma_alloc_coherent() in the architecture is broken. >> Hi Arnd, Flush cache is necessary for some performance reason on this device. Thanks, Lixu
