From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
On some architectures (e.g. arm64), ____cachline_aligned only aligns
to the cacheline size of the L1 cache size. L1_CACHE_BYTES in
arch64/include/asm/cache.h Unfortunately DMA safety on these
architectures requires the buffer no share a last level cache cacheline
given by ARCH_DMA_MINALIGN which has a greater granularity.
ARCH_DMA_MINALIGN is not defined for all architectures, but when it is
defined it is used to set the size of ARCH_KMALLOC_MINALIGN
to allow DMA safe buffer allocations.
As such the correct alignment requirement is
__aligned(ARCH_KMALLOC_MINALIGN).
This has recently been fixed in other subsystems such as IIO.
This is probably not a fix as such, because likely this particular
device is only used on devices where the given alignment is sufficient.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
Cc: Daniel Hung-yu Wu <hywu@xxxxxxxxxx>
---
drivers/input/misc/atmel_captouch.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/input/misc/atmel_captouch.c b/drivers/input/misc/atmel_captouch.c
index 051aded6815a..9681c763356c 100644
--- a/drivers/input/misc/atmel_captouch.c
+++ b/drivers/input/misc/atmel_captouch.c
@@ -71,7 +71,7 @@ struct atmel_captouch_device {
u32 num_btn;
u32 keycodes[MAX_NUM_OF_BUTTONS];
u8 prev_btn;
- u8 xfer_buf[8] ____cacheline_aligned;
+ u8 xfer_buf[8] __aligned(ARCH_KMALLOC_MINALIGN);
};
/*
--
2.38.1
