From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
On some architectures (e.g. arm64), ____cachline_aligned only aligns
to the cacheline size of the L1 cache size. L1_CACHE_BYTES in
arch64/include/asm/cache.h Unfortunately DMA safety on these
architectures requires the buffer no share a last level cache cacheline
given by ARCH_DMA_MINALIGN which has a greater granularity.
ARCH_DMA_MINALIGN is not defined for all architectures, but when it is
defined it is used to set the size of ARCH_KMALLOC_MINALIGN
to allow DMA safe buffer allocations.
As such the correct alignment requirement is
__aligned(ARCH_KMALLOC_MINALIGN).
This has recently been fixed in other subsystems such as IIO.
Fixes tag is imprecise as there may have been no architectures where the
two alignments differed at the time of that patch.
Fixes: 3843384a0554 ("Input: ad7877 - keep dma rx buffers in seperate cache lines")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
Cc: Michael Hennerich <michael.hennerich@xxxxxxxxxx>
---
drivers/input/touchscreen/ad7877.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/input/touchscreen/ad7877.c b/drivers/input/touchscreen/ad7877.c
index 08f5372f0bfd..eaf11dffb28e 100644
--- a/drivers/input/touchscreen/ad7877.c
+++ b/drivers/input/touchscreen/ad7877.c
@@ -150,7 +150,7 @@ struct ser_req {
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
*/
- u16 sample ____cacheline_aligned;
+ u16 sample __aligned(ARCH_KMALLOC_MINALIGN);
};
struct ad7877 {
@@ -189,7 +189,7 @@ struct ad7877 {
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
*/
- u16 conversion_data[AD7877_NR_SENSE] ____cacheline_aligned;
+ u16 conversion_data[AD7877_NR_SENSE] __aligned(ARCH_KMALLOC_MINALIGN);
};
static bool gpio3;
--
2.38.1
