On 05/18/2018 01:20 PM, Andy Shevchenko wrote:
On Fri, 2018-05-18 at 11:37 +0300, Andy Shevchenko wrote:
On Fri, 2018-05-18 at 09:48 +0200, Hans de Goede wrote:
Could it be the i2c input clock definition in drivers/mfd/intel-
lpss-
pci.c
is also wrong for Apollo Lake (N3450) ? There are lots of people
having
various issues with i2c attached touchpads on Apollo Lake devices,
this bug:
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1728244
Is sort of a collection bug for these. Various models laptops, lots
of
reporters. Note not sure thie is an i2c-designware issue, but it
would
be good to double check the input clock on Apollo Lake.
I've checked the datasheet and the datasheet mentions 133MHz as
"serial input clk" in the lpio_bxt_regs Registers Summary, which is
also part of the LPSS, no clk is mentioned in the "Summary of
DW_apb_i2c_mem_map_DW_apb_i2c_addr_block1 Registers".
The internal datasheet we have access to mentioned in this case for
Broxton and Cannonlake together. So, your assumption might be quite
close to the truth and the issue is inherited from Broxton.
Nope. The specification I have mention the I2C input clock in Broxton is
fixed 133 MHz but in Cannon Lake it is derived through non-SW visible
divider.
Hans, can your reporters try the following patch? Depending on the
result I may send it out ASAP.
--- a/drivers/mfd/intel-lpss-pci.c
+++ b/drivers/mfd/intel-lpss-pci.c
@@ -120,7 +120,7 @@ static struct property_entry apl_i2c_properties[] =
{
};
static const struct intel_lpss_platform_info apl_i2c_info = {
- .clk_rate = 133000000,
+ .clk_rate = 216000000,
.properties = apl_i2c_properties,
};
Nack. The Apollo Lake HW here shows expected I2C bus clock on
oscilloscope so it is indeed clocked at 133 MHz.
--
Jarkko
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