Hi Jarkko, et.al.,
On 17-05-18 09:48, Jarkko Nikula wrote:
Hi
On 05/15/2018 01:20 PM, Jarkko Nikula wrote:
On 05/15/2018 06:22 AM, Chris Chiu wrote:
What if I change the 120MHz to 180MHz and then make sure that the I2C operates
in target FS mode frequency 400kHz via scope? Would there be any side effect?
Maybe some other busses frequency could be also affected and causing some other
component malfunction?
Should be safe. It is only clock rate information when registering a fixed clock with known rate in intel-lpss.c and i2c-designware uses that info when calculating the timing parameters. I.e. it doesn't change any internal clocks.
I'm trying to find a contact who can confirm what is the expected rate of I2C input clock and is it common to all Cannon Lake HW.
I got confirmation that input clock is actually even higher 216 Mhz.
While checking does it cover all of those CNL CNL-LP and CNL-H PCI IDs may I add your Jian-Hong, Chris and Daniel email addresses to Repored-by tags in a fix patch?
Could it be the i2c input clock definition in drivers/mfd/intel-lpss-pci.c
is also wrong for Apollo Lake (N3450) ? There are lots of people having
various issues with i2c attached touchpads on Apollo Lake devices, this bug:
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1728244
Is sort of a collection bug for these. Various models laptops, lots of
reporters. Note not sure thie is an i2c-designware issue, but it would
be good to double check the input clock on Apollo Lake.
I've checked the datasheet and the datasheet mentions 133MHz as
"serial input clk" in the lpio_bxt_regs Registers Summary, which is
also part of the LPSS, no clk is mentioned in the "Summary of
DW_apb_i2c_mem_map_DW_apb_i2c_addr_block1 Registers".
Regards,
Hans
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