On Thu, May 17, 2018 at 3:48 PM, Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx> wrote: > Hi > > On 05/15/2018 01:20 PM, Jarkko Nikula wrote: >> >> On 05/15/2018 06:22 AM, Chris Chiu wrote: >>> >>> What if I change the 120MHz to 180MHz and then make sure that the I2C >>> operates >>> in target FS mode frequency 400kHz via scope? Would there be any side >>> effect? >>> Maybe some other busses frequency could be also affected and causing some >>> other >>> component malfunction? >>> >> Should be safe. It is only clock rate information when registering a fixed >> clock with known rate in intel-lpss.c and i2c-designware uses that info when >> calculating the timing parameters. I.e. it doesn't change any internal >> clocks. >> >> I'm trying to find a contact who can confirm what is the expected rate of >> I2C input clock and is it common to all Cannon Lake HW. >> > I got confirmation that input clock is actually even higher 216 Mhz. > > While checking does it cover all of those CNL CNL-LP and CNL-H PCI IDs may I > add your Jian-Hong, Chris and Daniel email addresses to Repored-by tags in a > fix patch? > > -- > Jarkko No problem. Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-input" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
