On Fri, 10 Jan 2025 11:24:20 +0100 Angelo Dureghello <adureghello@xxxxxxxxxxxx> wrote: > From: Angelo Dureghello <adureghello@xxxxxxxxxxxx> > > A new FPGA HDL has been developed from ADI to support ad354xr > devices. > > Add support for ad3541r and ad3542r with following additions: > > - use common device_info structures for hs and non hs drivers, > - DMA buffering, use DSPI mode for ad354xr and QSPI for ad355xr, > - change sample rate to respect number of lanes. > > Signed-off-by: Angelo Dureghello <adureghello@xxxxxxxxxxxx> I think the question I posted on v2 (missing there was a v3) still applies. Please check that thread. Jonathan
