On Wed, Dec 18, 2024 at 10:01:49AM +0100, Fabrice Gasnier wrote:
> diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
> index 17e591f61efb..99383e09920e 100644
> --- a/drivers/pwm/pwm-stm32.c
> +++ b/drivers/pwm/pwm-stm32.c
> @@ -19,6 +19,7 @@
> #define CCMR_CHANNEL_SHIFT 8
> #define CCMR_CHANNEL_MASK 0xFF
> #define MAX_BREAKINPUT 2
> +#define MAX_PWM_OUTPUT 4
I would prefer a less generic name. Something like STM32_PWM_MAX_OUTPUT.
> struct stm32_breakinput {
> u32 index;
> [...]
> @@ -790,11 +800,31 @@ static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
> priv->have_complementary_output = (ccer != 0);
> }
>
> -static unsigned int stm32_pwm_detect_channels(struct regmap *regmap,
> +static unsigned int stm32_pwm_detect_channels(struct stm32_timers *ddata,
> unsigned int *num_enabled)
> {
> + struct regmap *regmap = ddata->regmap;
> u32 ccer, ccer_backup;
>
> + if (ddata->ipidr) {
> + unsigned int npwm = 0;
No need to initialize npwm.
> + u32 val;
> +
> + /* Simply deduce from HWCFGR the number of outputs (MP25). */
> + regmap_read(regmap, TIM_HWCFGR1, &val);
> +
> + /*
> + * Timers may have more capture/compare channels than the
> + * actual number of PWM channel outputs (e.g. TIM_CH[1..4]).
> + */
> + npwm = FIELD_GET(TIM_HWCFGR1_NB_OF_CC, val);
> +
> + regmap_read(regmap, TIM_CCER, &ccer);
> + *num_enabled = hweight32(ccer & TIM_CCER_CCXE);
So the part that determines *num_enabled is the same for both variants.
Maybe it's possible to share the code for that?
> + return npwm < MAX_PWM_OUTPUT ? npwm : MAX_PWM_OUTPUT;
> + }
> +
> /*
> * If channels enable bits don't exist writing 1 will have no
> * effect so we can detect and count them.
Best regards
Uwe
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