From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
The ADC on the Renesas RZ/G3S SoC includes an additional channel (channel
8) dedicated to reading temperature values from the Thermal Sensor Unit
(TSU). There is a direct in-SoC connection between the ADC and TSU IPs.
To read the temperature reported by the TSU, a different sampling rate
(compared to channels 0-7) must be configured in the ADM3 register.
The rzg2l_adc driver has been updated to support reading the TSU
temperature.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---
drivers/iio/adc/rzg2l_adc.c | 81 +++++++++++++++++++++++++++----------
1 file changed, 60 insertions(+), 21 deletions(-)
diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index aff41152ebf8..f938b0f9a795 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -55,7 +55,8 @@
/**
* struct rzg2l_adc_hw_params - ADC hardware specific parameters
- * @default_adsmp: default ADC sampling period (see ADM3 register)
+ * @default_adsmp: default ADC sampling period (see ADM3 register); index 0 is
+ * used for voltage channels, index 1 is used for temperature channel
* @adsmp_mask: ADC sampling period mask (see ADM3 register)
* @adint_inten_mask: conversion end interrupt mask (see ADINT register)
* @default_adcmp: default ADC cmp (see ADM3 register)
@@ -63,7 +64,7 @@
* @adivc: specifies if ADVIC register is available
*/
struct rzg2l_adc_hw_params {
- u16 default_adsmp;
+ u16 default_adsmp[2];
u16 adsmp_mask;
u16 adint_inten_mask;
u8 default_adcmp;
@@ -87,15 +88,26 @@ struct rzg2l_adc {
struct mutex lock;
};
-static const char * const rzg2l_adc_channel_name[] = {
- "adc0",
- "adc1",
- "adc2",
- "adc3",
- "adc4",
- "adc5",
- "adc6",
- "adc7",
+/**
+ * struct rzg2l_adc_channel - ADC channel descriptor
+ * @name: ADC channel name
+ * @type: ADC channel type
+ */
+struct rzg2l_adc_channel {
+ const char * const name;
+ enum iio_chan_type type;
+};
+
+static const struct rzg2l_adc_channel rzg2l_adc_channels[] = {
+ { "adc0", IIO_VOLTAGE },
+ { "adc1", IIO_VOLTAGE },
+ { "adc2", IIO_VOLTAGE },
+ { "adc3", IIO_VOLTAGE },
+ { "adc4", IIO_VOLTAGE },
+ { "adc5", IIO_VOLTAGE },
+ { "adc6", IIO_VOLTAGE },
+ { "adc7", IIO_VOLTAGE },
+ { "adc8", IIO_TEMP },
};
static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
@@ -161,7 +173,7 @@ static void rzg2l_set_trigger(struct rzg2l_adc *adc)
rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
}
-static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
+static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch, enum iio_chan_type type)
{
const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
u32 reg;
@@ -177,6 +189,15 @@ static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
reg |= BIT(ch);
rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
+ reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
+ reg &= ~hw_params->adsmp_mask;
+ /*
+ * type could be IIO_VOLTAGE = 0 or IIO_TEMP = 9. Divide to 8 to get
+ * index 0 or 1 depending on the channel type.
+ */
+ reg |= hw_params->default_adsmp[type / 8];
+ rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
+
/*
* Setup ADINT
* INTS[31] - Select pulse signal
@@ -192,7 +213,8 @@ static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
return 0;
}
-static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
+static int rzg2l_adc_conversion(struct iio_dev *indio_dev, enum iio_chan_type type,
+ struct rzg2l_adc *adc, u8 ch)
{
const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
struct device *dev = indio_dev->dev.parent;
@@ -202,7 +224,7 @@ static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc
if (ret)
return ret;
- ret = rzg2l_adc_conversion_setup(adc, ch);
+ ret = rzg2l_adc_conversion_setup(adc, ch, type);
if (ret)
goto rpm_put;
@@ -238,13 +260,27 @@ static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,
return -EINVAL;
mutex_lock(&adc->lock);
- ret = rzg2l_adc_conversion(indio_dev, adc, ch);
+ ret = rzg2l_adc_conversion(indio_dev, chan->type, adc, ch);
if (!ret)
*val = adc->last_val[ch];
mutex_unlock(&adc->lock);
return ret ? ret : IIO_VAL_INT;
+ case IIO_CHAN_INFO_PROCESSED:
+ if (chan->type != IIO_TEMP)
+ return -EINVAL;
+
+ mutex_lock(&adc->lock);
+ ret = rzg2l_adc_conversion(indio_dev, chan->type, adc, ch);
+ if (!ret) {
+ /* Convert it to mili Celsius. */
+ *val = adc->last_val[ch] * 1000;
+ }
+ mutex_unlock(&adc->lock);
+
+ return ret ? ret : IIO_VAL_INT;
+
default:
return -EINVAL;
}
@@ -254,7 +290,7 @@ static int rzg2l_adc_read_label(struct iio_dev *iio_dev,
const struct iio_chan_spec *chan,
char *label)
{
- return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]);
+ return sysfs_emit(label, "%s\n", rzg2l_adc_channels[chan->channel].name);
}
static const struct iio_info rzg2l_adc_iio_info = {
@@ -332,11 +368,14 @@ static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l
if (channel >= hw_params->num_channels)
return -EINVAL;
- chan_array[i].type = IIO_VOLTAGE;
+ chan_array[i].type = rzg2l_adc_channels[channel].type;
chan_array[i].indexed = 1;
chan_array[i].channel = channel;
- chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
- chan_array[i].datasheet_name = rzg2l_adc_channel_name[channel];
+ if (rzg2l_adc_channels[channel].type == IIO_VOLTAGE)
+ chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
+ else
+ chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED);
+ chan_array[i].datasheet_name = rzg2l_adc_channels[channel].name;
i++;
}
@@ -386,7 +425,7 @@ static int rzg2l_adc_hw_init(struct device *dev, struct rzg2l_adc *adc)
reg &= ~RZG2L_ADM3_ADCMP_MASK;
reg &= ~hw_params->adsmp_mask;
reg |= FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, hw_params->default_adcmp) |
- hw_params->default_adsmp;
+ hw_params->default_adsmp[0];
rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
@@ -479,7 +518,7 @@ static int rzg2l_adc_probe(struct platform_device *pdev)
static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
.num_channels = 8,
.default_adcmp = 0xe,
- .default_adsmp = 0x578,
+ .default_adsmp = { 0x578 },
.adsmp_mask = GENMASK(15, 0),
.adint_inten_mask = GENMASK(7, 0),
.adivc = true
--
2.39.2
