On Mon, 9 Sep 2024 13:39:26 +0200 Angelo Dureghello <adureghello@xxxxxxxxxxxx> wrote: > On 08/09/24 2:29 PM, Jonathan Cameron wrote: > > On Thu, 05 Sep 2024 17:17:31 +0200 > > Angelo Dureghello <adureghello@xxxxxxxxxxxx> wrote: > > > >> From: Angelo Dureghello <adureghello@xxxxxxxxxxxx> > >> > >> There is a version AXI DAC IP block (for FPGAs) that provides > >> a physical bus for AD3552R and similar chips. This can be used > >> instead of a typical SPI controller to be able to use the chip > >> in ways that typical SPI controllers are not capable of. > >> > >> The binding is modified so that either the device is a SPI > >> peripheral or it uses an io-backend. > >> > >> Signed-off-by: Angelo Dureghello <adureghello@xxxxxxxxxxxx> > >> > >> required: > >> - compatible > >> - - reg > >> - - spi-max-frequency > > Sort of feels like both reg and spi-max-frequency > > are valid things to specify. > > This specific backend IP generates a fixed non-configurable clock > frequency, so i don't think the spi-max-frequency is needed. Ah fair enough. > > > > Maybe we have an excellent IP and dodgy wiring so want > > to clamp the frequency (long term - don't need to support > > in the driver today). > > > > Maybe we have an axi_dac IP that supports multiple > > front end devices? So maybe just keep reg? > > yes, this is what i am wondering now too, i simplified with just one > frontend node, are multimple frontends (and so reg property) needed ? It does little harm to have one. So I'd say keep it as required. Detection of what is required should be based on something more specific than reg being there or not. Jonathan
