On Fri, Sep 06, 2024 at 09:50:30AM +0100, Conor Dooley wrote: > On Thu, Sep 05, 2024 at 11:50:45AM +0200, Nuno Sá wrote: > > On Fri, 2024-08-30 at 16:33 +0100, Conor Dooley wrote: > > > On Fri, Aug 30, 2024 at 10:19:49AM +0200, Angelo Dureghello wrote: > > > > > > + maxItems: 1 > > > > > > + description: | > > > > > > + Configure bus type: > > > > > > + - 0: none > > > > > > + - 1: qspi > > > > > > Also, re-reading the cover letter, it says "this platform driver uses a 4 > > > lanes parallel bus, plus a clock line, similar to a qspi." > > > I don't think we should call this "qspi" if it is not actually qspi, > > > that's just confusing. > > > > > > > Just by looking at the datasheet it feels like typical qspi to be honest. And, > > fwiw, even if not really qspi, this is how the datasheet names the interface. > > Right, just a phrasing issue in the cover letter I guess :) The other thing that this brings into question, and I forget if I said it before (perhaps to David on IRC) was whether or not the ADC/DAC needs to be a child of the backend, if the backend is providing the SPI bus that the device is attached to. Why would it not be the case, if as you say, it appears to be a real qspi controller?
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