On Thu, 2024-07-18 at 00:25 +0300, Alisa-Dariana Roman wrote: > There are actually 4 configuration modes of clock source for AD719X > devices. Either a crystal can be attached externally between MCLK1 and > MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 > pin. The other 2 modes make use of the 4.92MHz internal clock. > > Undocumented properties adi,int-clock-output-enable and adi,clock-xtal > still supported for backward compatibility, but their use is highly > discouraged. Use cleaner alternative of configuring external clock by > using clock names mclk and xtal. > > Functionality of AD7192_CLK_INT_CO will be implemented in complementary > patch by adding clock provider. > > Signed-off-by: Alisa-Dariana Roman <alisa.roman@xxxxxxxxxx> > --- LGTM, Reviewed-by: Nuno Sa <nuno.sa@xxxxxxxxxx>
