Internal clock of AD719X devices can be made available on MCLK2 pin. Add
clock provider to support this functionality.
Modify second example to showcase this mode.
Signed-off-by: Alisa-Dariana Roman <alisa.roman@xxxxxxxxxx>
---
.../devicetree/bindings/iio/adc/adi,ad7192.yaml | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
index 67384bed4cd3..e31436484372 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
@@ -42,13 +42,17 @@ properties:
description:
Optionally, either a crystal can be attached externally between MCLK1 and
MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2
- pin. If absent, internal 4.92MHz clock is used.
+ pin. If absent, internal 4.92MHz clock is used, which can be made
+ available on MCLK2 pin.
clock-names:
enum:
- xtal
- mclk
+ "#clock-cells":
+ const: 0
+
interrupts:
maxItems: 1
@@ -204,8 +208,7 @@ examples:
spi-max-frequency = <1000000>;
spi-cpol;
spi-cpha;
- clocks = <&ad7192_mclk>;
- clock-names = "mclk";
+ #clock-cells = <0>;
interrupts = <25 0x2>;
interrupt-parent = <&gpio>;
aincom-supply = <&aincom>;
--
2.34.1
