On Mon, May 6, 2024 at 9:50 AM Nuno Sa via B4 Relay <devnull+nuno.sa.analog.com@xxxxxxxxxx> wrote: > > From: Nuno Sa <nuno.sa@xxxxxxxxxx> > > We enabling the core, make sure DRP (Dynamic Reconfiguration Port) s/We/When/ > is locked. Most of the designs don't really use it but we still get the > lock bit set. So let's do it all the time so the code is generic. > > While at it add proper mutex guards as we should not be able to disable > the core in the middle of enabling it. Also reduce the timeout time to 1 > microsecond as it seems to be enough and goes in line with what we have > on the similar DAC core (adi-axi-dac). > > Signed-off-by: Nuno Sa <nuno.sa@xxxxxxxxxx> > --- > drivers/iio/adc/adi-axi-adc.c | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c > index 0cf0d81358fd5..782d8813bb43b 100644 > --- a/drivers/iio/adc/adi-axi-adc.c > +++ b/drivers/iio/adc/adi-axi-adc.c > @@ -42,6 +42,9 @@ > #define ADI_AXI_ADC_REG_CTRL 0x0044 > #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) > > +#define AXI_ADC_DRP_STATUS 0x0074 call it AXI_ADC_REG_DRP_STATUS for consistency? > +#define AXI_ADC_DRP_LOCKED BIT(17) > + > /* ADC Channel controls */ > > #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
