As specified by the datasheet we should write the value 0x3 (enable plus tracking gain) into the MU_CNT1 register during the MU lock phase. Currently we were only setting the enable bit (bit 0) as the tracking gain default value is already set to 1. While we should be mostly fine in assuming the tracking gain will have the value it should, better to explicitly write it. On top of that the datasheet also states to re-attempt the writes in case the lock fails which we were not doing for the tracking gain bit. Lastly, the recommended value for the MU phase slope lock (bit 6) is 0 but for some reason the default value is 1 and hence, we were not changing it accordingly. Note there was no problem with the MU lock mechanism so this is not being treated as a fix but rather an improvement. Signed-off-by: Nuno Sa <nuno.sa@xxxxxxxxxx> --- drivers/iio/dac/ad9739a.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/iio/dac/ad9739a.c b/drivers/iio/dac/ad9739a.c index ff33120075bf..f56eabe53723 100644 --- a/drivers/iio/dac/ad9739a.c +++ b/drivers/iio/dac/ad9739a.c @@ -45,6 +45,7 @@ #define AD9739A_REG_MU_DUTY 0x25 #define AD9739A_REG_MU_CNT1 0x26 #define AD9739A_MU_EN_MASK BIT(0) +#define AD9739A_MU_GAIN_MASK BIT(1) #define AD9739A_REG_MU_CNT2 0x27 #define AD9739A_REG_MU_CNT3 0x28 #define AD9739A_REG_MU_CNT4 0x29 @@ -220,8 +221,8 @@ static int ad9739a_init(struct device *dev, const struct ad9739a_state *st) return ret; /* Enable the Mu controller search and track mode. */ - ret = regmap_set_bits(st->regmap, AD9739A_REG_MU_CNT1, - AD9739A_MU_EN_MASK); + ret = regmap_write(st->regmap, AD9739A_REG_MU_CNT1, + AD9739A_MU_EN_MASK | AD9739A_MU_GAIN_MASK); if (ret) return ret; --- base-commit: b22457f6c572c1b453207d13613a4e476d3dd0fb change-id: 20240429-ad9739a-improv-adeda16e0dd5 -- Thanks! - Nuno Sá
