On Sun, 11 Feb 2024 11:03:43 -0600 David Lechner <dlechner@xxxxxxxxxxxx> wrote: > On Sat, Feb 10, 2024 at 11:47 AM Jonathan Cameron <jic23@xxxxxxxxxx> wrote: > > > > On Tue, 6 Feb 2024 11:26:00 -0600 > > David Lechner <dlechner@xxxxxxxxxxxx> wrote: > > > > > This adds a driver for the Analog Devices Inc. AD7944, AD7985, and > > > AD7986 ADCs. These are a family of pin-compatible ADCs that can sample > > > at rates up to 2.5 MSPS. > > > > > > The initial driver adds support for sampling at lower rates using the > > > usual IIO triggered buffer and can handle all 3 possible reference > > > voltage configurations. > > > > > > Signed-off-by: David Lechner <dlechner@xxxxxxxxxxxx> > > > > > > The one thing in here that will probably bite if this gets much use of > > different boards is the use of non multiple of 8 word sizes. > > > > Often we can get away with padding those with trailing clocks. > > Any idea if that is safe here? > > We can probably get away with it on these chips. The ultimate goal > here, though, is to get these chips working a max sample rate which > only has a few 10s of nanoseconds of wiggle room between SPI > transfers. So I would rather have a bit more play in the timing than > try to support generic SPI controllers. > Would just be a case of providing a fallback. If you have a good spi controller then you get better data rats. Meh, can be added later when someone needs this. We've done that a few times before. Jonathan
