> > > > >>> + spinlock_t irq_busy_lock; /* Handshake between SPI and DRDY irqs */ > >>> + int rdata_xfer_busy; > >>> + > >>> + /* Temporary storage for demuxing data after SPI transfer */ > >>> + u32 bounce_buffer[ADS1298_MAX_CHANNELS]; > >>> + > >>> + /* For synchronous SPI exchanges (read/write registers) */ > >>> + u8 cmd_buffer[ADS1298_SPI_CMD_BUFFER_SIZE] __aligned(IIO_DMA_MINALIGN); > >>> + > >>> + /* Buffer used for incoming SPI data */ > >>> + u8 rx_buffer[ADS1298_SPI_RDATA_BUFFER_SIZE]; > > Cacheline aligned? > > I see the cmd_buffer, but shouldn't this be also aligned? > > I understood from Jonathan that that wasn't needed... "My" SPI > controller is rather dumb and doesn't even have DMA. > > Will take a closer look though. It should be fine. The aim here is to ensure that nothing access data in the same cacheline from the CPU side whilst DMA is ongoing (and unwanted write backs of stale data can occur). As long at the handling isn't very complex, a single marking of the first buffer used for DMA (and being sure there is nothing other than other DMA buffers after it the same cacheline (potentially multiple lines) is enough. So the __aligend(IIO_DMA_MINALIGN) on cmd_buffer should work for allt hese buffers.
