On Sun, 2024-01-21 at 16:12 +0000, Jonathan Cameron wrote: > On Wed, 17 Jan 2024 14:10:49 +0100 > Nuno Sa <nuno.sa@xxxxxxxxxx> wrote: > > > Aligning the buffer to the L1 cache is not sufficient in some platforms > > as they might have larger cacheline sizes for caches after L1 and thus, > > we can't guarantee DMA safety. > > > > That was the whole reason to introduce IIO_DMA_MINALIGN in [1]. Do the same > > for the sigma_delta ADCs. > > > > [1]: https://lore.kernel.org/linux-iio/20220508175712.647246-2-jic23@xxxxxxxxxx/ > > > > Fixes: ccd2b52f4ac6 ("staging:iio: Add common ADIS library") > > Signed-off-by: Nuno Sa <nuno.sa@xxxxxxxxxx> > Guess I didn't look in the main headers :( > Not many users anyways. Doing a git grep shows: git grep "____cacheline_aligned" include/linux/iio/ include/linux/iio/adc/ad_sigma_delta.h:102: uint8_t tx_buf[4] ____cacheline_aligned; include/linux/iio/common/st_sensors.h:261: char buffer_data[ST_SENSORS_MAX_BUFFER_SIZE] ____cacheline_aligned; include/linux/iio/imu/adis.h:134: u8 tx[10]____cacheline_aligned; So we are only missing the st header. I can send patch for it later today. - Nuno Sá
