On Wed, 17 Jan 2024 13:41:03 +0100 Nuno Sa <nuno.sa@xxxxxxxxxx> wrote: > Aligning the buffer to the L1 cache is not sufficient in some platforms > as they might have larger cacheline sizes for caches after L1 and thus, > we can't guarantee DMA safety. > > That was the whole reason to introduce IIO_DMA_MINALIGN in [1]. Do the same > for the sigma_delta ADCs. > > [1]: https://lore.kernel.org/linux-iio/20220508175712.647246-2-jic23@xxxxxxxxxx/ > Fixes: 0fb6ee8d0b5e ("iio: ad_sigma_delta: Don't put SPI transfer buffer on the stack") > Signed-off-by: Nuno Sa <nuno.sa@xxxxxxxxxx> Applied to the fixes-togreg branch of iio.git and marked for stable. Thanks, Jonathan > --- > include/linux/iio/adc/ad_sigma_delta.h | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/include/linux/iio/adc/ad_sigma_delta.h b/include/linux/iio/adc/ad_sigma_delta.h > index 7852f6c9a714..719cf9cc6e1a 100644 > --- a/include/linux/iio/adc/ad_sigma_delta.h > +++ b/include/linux/iio/adc/ad_sigma_delta.h > @@ -8,6 +8,8 @@ > #ifndef __AD_SIGMA_DELTA_H__ > #define __AD_SIGMA_DELTA_H__ > > +#include <linux/iio/iio.h> > + > enum ad_sigma_delta_mode { > AD_SD_MODE_CONTINUOUS = 0, > AD_SD_MODE_SINGLE = 1, > @@ -99,7 +101,7 @@ struct ad_sigma_delta { > * 'rx_buf' is up to 32 bits per sample + 64 bit timestamp, > * rounded to 16 bytes to take into account padding. > */ > - uint8_t tx_buf[4] ____cacheline_aligned; > + uint8_t tx_buf[4] __aligned(IIO_DMA_MINALIGN); > uint8_t rx_buf[16] __aligned(8); > }; > >
