According to the datasheet, the PWM high and low clock count values should be set to at least one. Therefore, setting the clock count register to 0 actually means 1 clock count. Signed-off-by: George Stark <GNStark@xxxxxxxxxxxxxx> Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx> --- This patch is based on currently unmerged patch by Heiner Kallweit https://lore.kernel.org/linux-amlogic/23fe625e-dc23-4db8-3dce-83167cd3b206@xxxxxxxxx --- diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 834acd7..57e7d9c 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -206,6 +206,11 @@ channel->pre_div = pre_div; channel->hi = duty_cnt; channel->lo = cnt - duty_cnt; + + if (channel->hi) + channel->hi--; + if (channel->lo) + channel->lo--; } return 0; @@ -340,7 +345,8 @@ channel->lo = FIELD_GET(PWM_LOW_MASK, value); channel->hi = FIELD_GET(PWM_HIGH_MASK, value); - state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi); + state->period = meson_pwm_cnt_to_ns(chip, pwm, + channel->lo + 1 + channel->hi + 1); state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi); return 0;
