On Wed, Feb 22, 2023 at 03:12:12PM +0000, Lee Jones wrote: > On Thu, 16 Feb 2023, Biju Das wrote: > > > Add RZ/G2L MTU3a counter driver. This IP supports the following > > phase counting modes on MTU1 and MTU2 channels > > > > 1) 16-bit phase counting modes on MTU1 and MTU2 channels. > > 2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels. > > > > This patch adds 3 counter value channels. > > count0: 16-bit phase counter value channel on MTU1 > > count1: 16-bit phase counter value channel on MTU2 > > count2: 32-bit phase counter value channel by cascading > > MTU1 and MTU2 channels. > > > > The external input phase clock pin for the counter value channels > > are as follows: > > count0: "MTCLKA-MTCLKB" > > count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" > > count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" > > > > Use the sysfs variable "external_input_phase_clock_select" to select the > > external input phase clock pin and "cascade_counts_enable" to enable/ > > disable cascading of channels. > > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > Reviewed-by: William Breathitt Gray <william.gray@xxxxxxxxxx> > > Hey William, > > Is this a review or an ack? > > It looks like there are deps on other patches in this set. It's likely > that the whole set with to in together via one tree (probably MFD), > which I can make happen with the appropriate maintainer acks. I reviewed just this patch in-depth so that's wherefore the Reviewed-by tag. However, I do approve of these changes so please apply my Ack as well if so neccessary to pick this up. Acked-by: William Breathitt Gray <william.gray@xxxxxxxxxx> One minor suggestion is to include MAINTAINERS entries for the new MTU3a core driver and PWM driver, but I'll yield to the respective subsystem maintainers regarding that matter.
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