RE: [PATCH v6 2/2] pwm: Add support for RZ/G2L GPT

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Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v6 2/2] pwm: Add support for RZ/G2L GPT
> 
> Hi Biju,
> 
> On Sat, Sep 24, 2022 at 6:10 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > Note:
> > I have a plan to develop another PWM driver using MTU IP on the same
> SoC.
> > The work is not started yet.
> 
> That is the MTU3, which seems to be a further evolution of the MTU2 in
> e.g. RZ/A1, which is already supported as a timer through the
> sh_mtu2 driver?

sh_mtu2 is just supports clock events. MTU2 is much powerful and we are
not supporting more advanced features like phase counting(counter framework),
PWM(frame wok) etc...

> 
> > For this IP, I planned to use MFD framework for the MTU driver and
> > Will add counter driver, timer driver(clock source, clock event) and
> > pwm driver as child devices.
> >
> > Currently the MFD driver and 16-Bit Phase Counting using counter
> > framework is almost done.
> 
> Do you really need an MFD? (MFDs trigger a red flag for me ;-) E.g.

Similar concept is already available in mainline[1].
See STM32 timers where there is an MFD driver supports timer, counter
And pwm as child devices.

[1] https://elixir.bootlin.com/linux/v6.0-rc5/C/ident/TIM_ARR

> there are two sets of bindings for renesas,tpu: when #pwm-cells is
> present, it is used for PWM, otherwise it is used as a timer.

[2]
Yes, we could encapsulate all in PWM. But then we need to call
Other susbsytem from pwm (eg:- counter and timer).

I am not sure, PWM subsystem people allows to call counter and
Timer subsystem calls from pwm driver?? If yes, then that will simplifies a lot.

[3]
I almost have an RFC ready for MFD + 16-bit phase counting mode
Using counter device with MTU3 which is tested on MTU{1,2} channels.

So basically, we need to decide whether to go with approach [2]
Or [3]??

Please share your views, I can post RFC patch to get a clear picture
if needed. Please let me know.

Cheers,
Biju





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