On 12/08/2022 14:51, Bough Chen wrote: >> -----Original Message----- >> From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> >> Sent: 2022年8月4日 15:11 >> To: Bough Chen <haibo.chen@xxxxxxx>; jic23@xxxxxxxxxx; lars@xxxxxxxxxx; >> robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; >> shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx >> Cc: kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx; dl-linux-imx >> <linux-imx@xxxxxxx>; linux-iio@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx >> Subject: Re: [PATCH 2/3] dt-bindings: iio: adc: Add binding documentation for >> NXP IMX93 ADC >> >> On 04/08/2022 03:05, Bough Chen wrote: >>>> -----Original Message----- >>>> From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> >>>> Sent: 2022年8月3日 18:20 >>>> To: Bough Chen <haibo.chen@xxxxxxx>; jic23@xxxxxxxxxx; >>>> lars@xxxxxxxxxx; >>>> robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; >>>> shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx >>>> Cc: kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx; dl-linux-imx >>>> <linux-imx@xxxxxxx>; linux-iio@xxxxxxxxxxxxxxx; >>>> devicetree@xxxxxxxxxxxxxxx >>>> Subject: Re: [PATCH 2/3] dt-bindings: iio: adc: Add binding >>>> documentation for NXP IMX93 ADC >>>> >>>> On 03/08/2022 11:12, haibo.chen@xxxxxxx wrote: >>>>> From: Haibo Chen <haibo.chen@xxxxxxx> >>>>> >>>>> The IMX93 SoC has a new ADC IP, so add binding documentation for NXP >>>>> IMX93 ADC. >>>>> >>>>> Signed-off-by: Haibo Chen <haibo.chen@xxxxxxx> >>>>> --- >>>>> .../bindings/iio/adc/nxp,imx93-adc.yaml | 65 >>>> +++++++++++++++++++ >>>>> 1 file changed, 65 insertions(+) >>>>> create mode 100644 >>>>> Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml >>>>> >>>>> diff --git >>>>> a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml >>>>> b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml >>>>> new file mode 100644 >>>>> index 000000000000..e0eac5aa81d7 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml >>>>> @@ -0,0 +1,65 @@ >>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 >>>>> +--- >>>>> +$id: >>>>> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fde >>>>> +vi >>>>> >>>> >> +cetree.org%2Fschemas%2Fiio%2Fadc%2Fnxp%2Cimx93-adc.yaml%23&d >>>> ata=0 >>>>> >>>> >> +5%7C01%7Chaibo.chen%40nxp.com%7Ca11cd128f8814929684b08da7539b >>>> dbc%7C68 >>>>> >>>> +6ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637951188101491669% >>>> 7CUnknown >>>>> >>>> +%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha >>>> WwiLC >>>>> >>>> >> +JXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=JFNr4telb4AovE62YaHQu >>>> KNr1ywL%2 >>>>> +Blc0dJMFNN1OA1U%3D&reserved=0 >>>>> +$schema: >>>>> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fde >>>>> +vi >>>>> >>>> >> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7Chaib >>>> o.che >>>>> >>>> +n%40nxp.com%7Ca11cd128f8814929684b08da7539bdbc%7C686ea1d3bc2 >>>> b4c6fa92c >>>>> >>>> +d99c5c301635%7C0%7C0%7C637951188101491669%7CUnknown%7CTWF >>>> pbGZsb3d8eyJ >>>>> >>>> >> +WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% >>>> 7C300 >>>>> >>>> >> +0%7C%7C%7C&sdata=A1PPlSkOsS7nWFOPAokyA1F8%2BYFSZj5dY%2FO >>>> blm0U4UA% >>>>> +3D&reserved=0 >>>>> + >>>>> +title: NXP ADC found on the imx93 SoC >>>> >>>> How different it is from ADC in imx8qxp? >>> >>> They are totally two different ADC IP, no similar with each other. >> >> Each submitter responds like that... how much different? What is different? >> Driver has lots of copied pieces, so actually could be unified as well. > > HI Krzysztof, > > Sorry for the delay, high loading on my current work. > > For the difference, in general, > First, the register define is totally different. > Second, the ADC architecture is different, For imx8qxp, it contains ADC input ctrl + ADC core + ADC out control > For imx93 ADC, it called SAR_ADC, contain ADCD + ADCA, in detail, it also contain calibration/self-test/watch dog timer IP logic, > Third, different conversion mode, 8QXP ADC support single and continue conversion, support average conversion. > For imx93 ADC, it support normal mode, include single and average conversion, inject mode, hardware trigger mode. > > These two drivers architecture looks similar, because they all under IIO subsystem. > > For 8qxp ADC, it's feature list in RM: > ? Support up to 16 analog inputs > ? Support five conversion pairs, can work simultaneously, with different conversion > priority. > ? Word size is 12-bits. > ? Support Single and Continue conversion. > ? Support Compare mode and channel auto disable if data match the requirement. > ? Support Average conversion, Support flexible 4, 8, 16, 32 number of conversion > data. > ? Configurable sample time and conversion speed / power. The ADC core clock can > vary from 300 kHz to 6 MHz, and the maximum sample rate is 1/6 ADC core clock. > ? Conversion complete, hardware average complete, compare, DMA, time out flag and > interrupt. > ? Automatic compare with interrupt for less than, greater than, and equal to, within > range, or out-of-range, programmable value. > > For imx93 ADC, it's feature list in RM > ? 4'd12-bit resolution > ?Multiple modes of starting conversion (Normal, Injected) > —Normal mode supports One-Shot and Scan (continuous) conversions > —Injected mode supports One-Shot conversions only > ?Software-initiated conversions in Normal and Injected modes, or external hardware trigger > ?Two different abort features for either a single or chain conversion in Normal and Injected modes > ?Independent data registers for each channel contain information about mode of conversion, data validity, overwrite status, and conversion data > ?Alternate analog watchdog thresholds (threshold selected through input ports) > ?Programmable DMA enables for each channel > ?Individual interrupt flags for the following conditions: > —End of conversion of a single channel for Normal and Injected modes > —End of chain conversion for both Normal and Injected modes > —Watchdog threshold violations > ?Programmable presampling for channels > ?Auto-Clock-Off feature for improved power performance > ?Power-Down mode to place the SAR_ADC in power-down state > ?Programmable clock prescaler for SAR_ADC (bus clock, or bus clock divided by two or four) > ?Software-initiated calibration > ?Self-test feature By pasting big pieces of description from RM you do not prove what are the differences and it is not my task to find that one line which shows the decisive difference (e.g. support or lack of support for DMA). Best regards, Krzysztof
