Hi Cosmin,
thanks for your patch!
On Fri, Jul 15, 2022 at 6:50 AM Cosmin Tanislav <demonsingur@xxxxxxxxx> wrote:
> AD4130-8 is an ultra-low power, high precision, measurement solution for
> low bandwidth battery operated applications.
>
> The fully integrated AFE (Analog Front-End) includes a multiplexer for up
> to 16 single-ended or 8 differential inputs, PGA (Programmable Gain
> Amplifier), 24-bit Sigma-Delta ADC, on-chip reference and oscillator,
> selectable filter options, smart sequencer, sensor biasing and excitation
> options, diagnostics, and a FIFO buffer.
>
> Signed-off-by: Cosmin Tanislav <cosmin.tanislav@xxxxxxxxxx>
> Reviewed-by: Andy Shevchenko <andy.shevchenko@xxxxxxxxx>
(...)
> +static int ad4310_parse_fw(struct iio_dev *indio_dev)
> +{
(...)
> + int_clk_out = device_property_read_bool(dev, "adi,int-clk-out");
> + if (st->mclk && int_clk_out)
> + return dev_err_probe(dev, -EINVAL,
> + "Cannot expose internal clock\n");
> +
> + device_property_read_u32(dev, "adi,ext-clk-freq-hz", &ext_clk_freq);
> + if (ext_clk_freq != AD4130_MCLK_FREQ_153_6KHZ &&
> + ext_clk_freq != AD4130_MCLK_FREQ_76_8KHZ)
> + return dev_err_probe(dev, -EINVAL,
> + "Invalid external clock frequency %u\n",
> + ext_clk_freq);
As mentioned in the bindings I think this is cheating. Just implement a real
clock abstraction and take the desired clock divider (1 or 2?) from the phandle.
See e.g.
commit 639d5661cc808057854681685ecb596406dbacce
"clk: ux500: Implement the missing CLKOUT clocks"
for an example, it is more complex so it should be a copy/paste/strip
exercise mostly.
Yours,
Linus Walleij
