On Sun, Jul 3, 2022 at 3:09 PM Patricio Moreno <pm.pato@xxxxxxxxx> wrote: > > Hello, > > I'm writing a driver for the TI ADS127x family of ADCs. The ads127x is a > 24 bit samples, 4/8 channels, ADC, which can be clocked, using SPI, with > up to 25 MHz. For what I've seen, I've followed a common approach within > the IIO ADC drivers, but I can't get it to work at high frequencies. > > I'm using the triggered buffers interface, with a RDY interrupt pin. The > problem I have is with timings. When the ADC sends the data ready > signal, my handler is called approximately 7µs later. This handler then > calls spi_read to get 24 bytes (8 3 bytes samples) and the kernel takes > a lot of time to read the SPI bus, actually, to *start* reading. > > I would really appreciate some guidance on how to deal with this issue. +Cc: maintainers and AD guys. I remember there was a discussion about supporting HiFreq ADCs in IIO and AFAIR there are some issues (and you probably need to use DMA in cyclic mode or so). ... > st->data.samples[i] = (b[3 * i] << 16) | (b[3 * i + 1] > << 8) | (b[3 * i + 2] << 0); JFYI: get_unaligned_be24() is what you need here. -- With Best Regards, Andy Shevchenko
