Re: [PATCH 01/10] regmap-irq: Add get_irq_reg to support unusual register layouts

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Guru Das Srinagesh <quic_gurus@xxxxxxxxxxx> writes:

> On Fri, Jun 03, 2022 at 02:57:05PM +0100, Aidan MacDonald wrote:
>> Add a new callback, get_irq_reg, for regmap IRQ chips, to support devices
>> with unusual register layouts. This is required in the rare cases where
>> the offset of an IRQ register is not constant with respect to the base
>> register. This is probably best illustrated with an example:
>> 
>>             mask    status
>>     IRQ0    0x40    0x44
>>     IRQ1    0x41    0x45
>>     IRQ2    0x42    0x46
>>     IRQ3    0x43    0x47
>>     IRQ4    0x4a    0x4d
>> 
>> If we set mask_base = 0x40 and status_base = 0x44, the offsets of each
>> register relative to the base are:
>> 
>>             mask    status
>>     IRQ0    0       0
>>     IRQ1    1       1
>>     IRQ2    2       2
>>     IRQ3    3       3
>>     IRQ4    10      9
>> 
>> The existing mapping mechanisms can't include IRQ4 in the same irqchip
>> as IRQ0-3 because the offset of IRQ4's register depends on which type
>> of register we're asking for, ie. which base register is used.
>> 
>> The get_irq_reg callback allows drivers to specify an arbitrary mapping
>> of (base register, register index) pairs to register addresses, instead
>> of the default linear mapping "base_register + register_index". This
>> allows unusual layouts, like the one above, to be handled using a single
>> regmap IRQ chip.
>> 
>> The drawback is that when get_irq_reg is used, it's impossible to use
>> bulk reads for status registers even if some of them are contiguous,
>> because the mapping is opaque to regmap-irq. This should be acceptable
>> for the case of a few infrequently-polled status registers.
>
> This patch does two things:
>
> 1. Add a new callback `get_irq_reg`
> 2. Replace unmask_offset calculation with call to sub_irq_reg()
>
> Could you please split the patch into two to better reflect this?
>
> Thank you.
>
> Guru Das.

No problem, I'll do that in my v2.

Regards,
Aidan



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