On 5/16/22 22:39, Yannick Brosseau wrote:
> The irq handler was only checking the mask for the first ADCs in the case of the
> F4 and H7 generation, since it was iterating up to the num_irq value. This patch add
> the maximum number of ADC in the common register, which map to the number of entries of
> eoc_msk and ovr_msk in stm32_adc_common_regs. This allow the handler to check all ADCs in
> that module.
>
> Tested on a STM32F429NIH6.
>
> Fixes: 695e2f5c289b ("iio: adc: stm32-adc: fix a regression when using dma and irq")
> Signed-off-by: Yannick Brosseau <yannick.brosseau@xxxxxxxxx>
Hi Yannick,
Feel free to add my:
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@xxxxxxxxxxx>
Thanks,
Fabrice
> ---
> drivers/iio/adc/stm32-adc-core.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
> index 142656232157..bb04deeb7992 100644
> --- a/drivers/iio/adc/stm32-adc-core.c
> +++ b/drivers/iio/adc/stm32-adc-core.c
> @@ -64,6 +64,7 @@ struct stm32_adc_priv;
> * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
> * @has_syscfg: SYSCFG capability flags
> * @num_irqs: number of interrupt lines
> + * @num_adcs: maximum number of ADC instances in the common registers
> */
> struct stm32_adc_priv_cfg {
> const struct stm32_adc_common_regs *regs;
> @@ -71,6 +72,7 @@ struct stm32_adc_priv_cfg {
> u32 max_clk_rate_hz;
> unsigned int has_syscfg;
> unsigned int num_irqs;
> + unsigned int num_adcs;
> };
>
> /**
> @@ -352,7 +354,7 @@ static void stm32_adc_irq_handler(struct irq_desc *desc)
> * before invoking the interrupt handler (e.g. call ISR only for
> * IRQ-enabled ADCs).
> */
> - for (i = 0; i < priv->cfg->num_irqs; i++) {
> + for (i = 0; i < priv->cfg->num_adcs; i++) {
> if ((status & priv->cfg->regs->eoc_msk[i] &&
> stm32_adc_eoc_enabled(priv, i)) ||
> (status & priv->cfg->regs->ovr_msk[i]))
> @@ -792,6 +794,7 @@ static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
> .clk_sel = stm32f4_adc_clk_sel,
> .max_clk_rate_hz = 36000000,
> .num_irqs = 1,
> + .num_adcs = 3,
> };
>
> static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
> @@ -800,6 +803,7 @@ static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
> .max_clk_rate_hz = 36000000,
> .has_syscfg = HAS_VBOOSTER,
> .num_irqs = 1,
> + .num_adcs = 2,
> };
>
> static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
> @@ -808,6 +812,7 @@ static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
> .max_clk_rate_hz = 40000000,
> .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
> .num_irqs = 2,
> + .num_adcs = 2,
> };
>
> static const struct of_device_id stm32_adc_of_match[] = {
