On Tue, May 03, 2022 at 10:58:32AM +0200, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
>
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1. Switch to the updated
> IIO_ALIGN definition.
>
> Update the comment to include 'may'.
>
> Fixes: 3691e5a69449 ("iio: adc: add driver for the ti-adc084s021 chip")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
> Cc: Mårten Lindahl <martenli@xxxxxxxx>
Acked-by: Mårten Lindahl <marten.lindahl@xxxxxxxx>
> ---
> drivers/iio/adc/ti-adc084s021.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iio/adc/ti-adc084s021.c b/drivers/iio/adc/ti-adc084s021.c
> index c9b5d9aec3dc..6464541319af 100644
> --- a/drivers/iio/adc/ti-adc084s021.c
> +++ b/drivers/iio/adc/ti-adc084s021.c
> @@ -32,10 +32,10 @@ struct adc084s021 {
> s64 ts __aligned(8);
> } scan;
> /*
> - * DMA (thus cache coherency maintenance) requires the
> + * DMA (thus cache coherency maintenance) may require the
> * transfer buffers to live in their own cache line.
> */
> - u16 tx_buf[4] ____cacheline_aligned;
> + u16 tx_buf[4] __aligned(IIO_ALIGN);
> __be16 rx_buf[5]; /* First 16-bits are trash */
> };
>
> --
> 2.36.0
>
