Hi Jonathan,
On Tue, May 03, 2022 at 09:58:27AM +0100, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
>
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1. Switch to the updated
> IIO_ALIGN definition.
>
> Update the comment to include 'may'.
>
> Fixes: a8e7e88df9ec ("iio: adc: Add Maxim MAX11100 driver")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
> Cc: Jacopo Mondi <jacopo+renesas@xxxxxxxxxx>
Thanks
Acked-by: Jacopo Mondi <jacopo@xxxxxxxxxx>
> ---
> drivers/iio/adc/max11100.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iio/adc/max11100.c b/drivers/iio/adc/max11100.c
> index eb1ce6a0315c..4766d45344f7 100644
> --- a/drivers/iio/adc/max11100.c
> +++ b/drivers/iio/adc/max11100.c
> @@ -33,10 +33,10 @@ struct max11100_state {
> struct spi_device *spi;
>
> /*
> - * DMA (thus cache coherency maintenance) requires the
> + * DMA (thus cache coherency maintenance) may require the
> * transfer buffers to live in their own cache lines.
> */
> - u8 buffer[3] ____cacheline_aligned;
> + u8 buffer[3] __aligned(IIO_ALIGN);
> };
>
> static const struct iio_chan_spec max11100_channels[] = {
> --
> 2.36.0
>
