Il giorno gio 17 feb 2022 alle ore 22:58 Peter Meerwald-Stadler
<pmeerw@xxxxxxxxxx> ha scritto:
>
> On Thu, 17 Feb 2022, Andrea Merello wrote:
>
> nice work, minor comments below
Thanks.
Just an inline comment; OK for all the rest.
[...]
> > +static bool bno055_regmap_writeable(struct device *dev, unsigned int reg)
> > +{
> > + /*
> > + * Unreadable registers are indeed reserved; there are no WO regs
> > + * (except for a single bit in SYS_TRIGGER register)
> > + */
> > + if (!bno055_regmap_readable(dev, reg))
> > + return false;
> > +
> > + /* data and status registers */
> > + if (reg >= BNO055_ACC_DATA_X_LSB_REG && reg <= BNO055_SYS_ERR_REG)
> > + return false;
> > +
> > + /* IDs areas */
>
> probably 'ID area'?
>
I'd say 'ID areas' then, because there are two zones in which
different IDs lay (one below the PAGESEL register that contains e.g.
SW ID, internal gyro ID, accell ID, and the other that contains the
chip UID)
> > + if (reg < BNO055_PAGESEL_REG ||
> > + (reg <= BNO055_UID_HIGHER_REG && reg >= BNO055_UID_LOWER_REG))
> > + return false;
> > +
> > + return true;
> > +}
> > +
