Hi Anand, url: https://github.com/0day-ci/linux/commits/Anand-Ashok-Dumbre/Add-Xilinx-AMS-Driver/20210625-023047 base: https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg config: microblaze-randconfig-m031-20210628 (attached as .config) compiler: microblaze-linux-gcc (GCC) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> Reported-by: Dan Carpenter <dan.carpenter@xxxxxxxxxx> smatch warnings: drivers/iio/adc/xilinx-ams.c:406 ams_enable_channel_sequence() warn: should '(((1))) << (indio_dev->channels[i]->scan_index)' be a 64 bit type? drivers/iio/adc/xilinx-ams.c:1126 ams_init_module() error: uninitialized symbol 'chan_node'. vim +406 drivers/iio/adc/xilinx-ams.c fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 392 static void ams_enable_channel_sequence(struct iio_dev *indio_dev) fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 393 { fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 394 int i; fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 395 unsigned long long scan_mask; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 396 struct ams *ams = iio_priv(indio_dev); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 397 fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 398 /* fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 399 * Enable channel sequence. First 22 bits of scan_mask represent fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 400 * PS channels, and next remaining bits represent PL channels. fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 401 */ fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 402 fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 403 /* Run calibration of PS & PL as part of the sequence */ fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 404 scan_mask = 0x1 | BIT(AMS_PS_SEQ_MAX); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 405 for (i = 0; i < indio_dev->num_channels; i++) fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 @406 scan_mask |= BIT(indio_dev->channels[i].scan_index); Since scan_mask is ull should we use BIT_ULL() instead of BIT()? (I haven't look at the context outside of this email so I don't know the value of indio_dev->num_channels). fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 407 fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 408 if (ams->ps_base) { fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 409 /* put sysmon in a soft reset to change the sequence */ fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 410 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 411 AMS_CONF1_SEQ_DEFAULT); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 412 fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 413 /* configure basic channels */ fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 414 writel(scan_mask & AMS_REG_SEQ0_MASK, fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 415 ams->ps_base + AMS_REG_SEQ_CH0); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 416 writel(AMS_REG_SEQ2_MASK & fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 417 (scan_mask >> AMS_REG_SEQ2_MASK_SHIFT), fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 418 ams->ps_base + AMS_REG_SEQ_CH2); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 419 fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 420 /* set continuous sequence mode */ fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 421 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 422 AMS_CONF1_SEQ_CONTINUOUS); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 423 } fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 424 fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 425 if (ams->pl_base) { fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 426 /* put sysmon in a soft reset to change the sequence */ fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 427 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 428 AMS_CONF1_SEQ_DEFAULT); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 429 fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 430 /* configure basic channels */ fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 431 scan_mask = scan_mask >> AMS_PS_SEQ_MAX; fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 432 writel(scan_mask & AMS_REG_SEQ0_MASK, fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 433 ams->pl_base + AMS_REG_SEQ_CH0); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 434 writel(AMS_REG_SEQ2_MASK & fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 435 (scan_mask >> AMS_REG_SEQ2_MASK_SHIFT), fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 436 ams->pl_base + AMS_REG_SEQ_CH2); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 437 writel(AMS_REG_SEQ1_MASK & fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 438 (scan_mask >> AMS_REG_SEQ1_MASK_SHIFT), fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 439 ams->pl_base + AMS_REG_SEQ_CH1); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 440 fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 441 /* set continuous sequence mode */ fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 442 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 443 AMS_CONF1_SEQ_CONTINUOUS); fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 444 } fa0ea7aaf7a9bf Anand Ashok Dumbre 2021-06-24 445 } --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
