Re: using dma buffers for SPI adcs

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Jonathan,

Thanks for the information. It appears my original email was sent with
an old @ieee.org alias, meaning I never received the reply since that
alias is currently inactive.

My end goal is get an 8-channel ADC working with >100ksps/channel.
That doesn't seem do-able without an FPGA/PRU/real-time coprocessor to
offload the SPI controller to for an IIO-based approach. So now I'm
researching how to do something similar, but with the ASoC framework
instead of iio, using a different ADC that supports DAIs like NXP SAI
and TI McASP. But I'm running into issues there too with learning how
to configure simple-sound-card and a dummy-codec, but I suppose my
questions there should to go to the ALSA mailing list.

Starting to wonder though if I do need to go PRU/real-time coprocessor
route e,g., Cortex-M4 on same die as microprocessor (e.g, IMX8 and M4,
STM32MP1 A7 w/ M4, AM3358 w/ PRU, etc.).

Thanks,
Alex.



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