Le 13/09/2019 à 09:24, Ardelean, Alexandru a écrit :
On Thu, 2019-09-12 at 16:43 +0200, Andrea Merello wrote:
[External]
This patch series fixes ad7949 driver incorrectly read data, simplify the
code, and enforces device timing constraints.
This has been tested on a UltraZed SOM + a custom carrier equipped with
several AD7689 A/Ds. Patches have been developed on a Xilinx upstream
kernel and then rebased on linux-next kernel.
Thanks for the patches.
Added Charles-Antoine to also take a look.
Apologies for not thinking of adding him sooner.
I typically try to review changes for ADI parts, but he wrote it, so he may have more input than I do.
Jonathan will likely also take a look.
If it's agreed, I would say to at least take the first patch ("iio: ad7949: kill pointless "readback"-handling code")
now and see about the rest.
The rest are a bit more open to discussion, so a v2 may happen.
Hi,
Don't worry. Due to the fact I don't have on my mail client access to
the whole discussions, I'm making a complete answer there based on the
archive of the mailing list. Sorry for that.
For the patch 1, I approve it too. This part of code is useless because
the feature was removed. RIP my code. :D
For the patch 2, the cache information was added due to comment from
Jonathan Cameron when I developed the driver. The comment was:
Look very carefully at the requirements for a buffer being passed
to spi_sync. It needs to be DMA safe. This one is not. The usual
way to do that easily is to put a cacheline aligned buffer in your
ad7949_adc_chip structure.
Lots of examples to copy, but it's also worth making sure you understand
why this is necessary.
For the endianess thing, it shouldn't be required to make an explicit
conversion into the driver. According to the spi.h documentation:
* In-memory data values are always in native CPU byte order, translated
* from the wire byte order (big-endian except with SPI_LSB_FIRST). So
* for example when bits_per_word is sixteen, buffers are 2N bytes long
* (@len = 2N) and hold N sixteen bit words in CPU byte order.
So from my point of view the SPI subsystem always converts to the right
endianess. We don't have to take care about it.
For patch 3, I didn't use delay_usecs fiels due to the timings
definition in the datasheet in "READ/WRITE SPANNING CONVERSION WITHOUT A
BUSY INDICATOR" mode. During the delay, the chip select line must be
released which is not the case when we use delay_usecs field. So I add
the delay instruction after the write step to be compliant with these
timings.
For patch 4, I explained a bit in the other thread. Maybe we have a
difference of behaviour due to the choice of the timings "modes"?
BTW, from my point of view the datasheet is not totally clear about the
timings and what is mandatory or not in the expected behaviour.
Regards,
Charles-Antoine Couret
