On Thu, 2019-09-12 at 16:43 +0200, Andrea Merello wrote:
> [External]
>
> Each time we need to read a sample the driver writes the CFG register
> (setting the channel to be read in such register) and then it performs
> another xfer to read the resulting value.
>
> This does not work correctly because while writing the CFG register the
> acquisition phase is ongoing using the _previous_ CFG settings. Then the
> device performs the conversion during xfer delay on the voltage stored
> duting the said acquisitaion phase. Finally the driver performs the read
> (during the next acquisition phase, which is the one done with the right
> settings) and it gets the last converted value, that is the wrong data.
>
> In case the configuration is not actually changed, then we still get
> correct data, but in case the configuration changes (and this happens e.g.
> switching the MUX on another channel), we get wrong data (data from the
> previously selected channel).
>
> This patch fixes this by performing one more "dummy" transfer in order to
> ending up in reading the data when it's really ready.
So, at power-up this chip seems to need 2 dummy reads to discard data.
Which seems to happen in ad7949_spi_init()
One thing that maybe could be optimized (for the driver), is in `ad7949_spi_read_channel()` to use the current-channel &
not do a SPI write to change the channel if it doesn't change.
Datasheets (in general) are not always obvious about describing chip behavior for SW (or for writing a driver), but I
would suspect that if you are reading garbage data, it could be that the channel has changed.
This is true for some other ADCs.
And requires testing for this one.
Added Charles-Antoine, since he wrote the driver.
Shoud have added him on the other patches as well, but I just remembered.
Thanks
Alex
>
> Signed-off-by: Andrea Merello <andrea.merello@xxxxxxxxx>
> ---
> drivers/iio/adc/ad7949.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/iio/adc/ad7949.c b/drivers/iio/adc/ad7949.c
> index 25d1e1b24257..b1dbe2075ca9 100644
> --- a/drivers/iio/adc/ad7949.c
> +++ b/drivers/iio/adc/ad7949.c
> @@ -85,6 +85,7 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
> unsigned int channel)
> {
> int ret;
> + int i;
> int bits_per_word = ad7949_adc->resolution;
> int mask = GENMASK(ad7949_adc->resolution, 0);
> struct spi_message msg;
> @@ -97,12 +98,19 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
> },
> };
>
> - ret = ad7949_spi_write_cfg(ad7949_adc,
> - channel << AD7949_OFFSET_CHANNEL_SEL,
> - AD7949_MASK_CHANNEL_SEL);
> - if (ret)
> - return ret;
> + /*
> + * 1: write CFG for sample 'n' and read garbage (sample n-2)
> + * 2: write something and read garbage (sample n-1)
> + */
> + for (i = 0; i < 2; i++) {
> + ret = ad7949_spi_write_cfg(ad7949_adc,
> + channel << AD7949_OFFSET_CHANNEL_SEL,
> + AD7949_MASK_CHANNEL_SEL);
> + if (ret)
> + return ret;
> + }
>
> + /* 3: write something and read data for sample 'n' */
> ad7949_adc->buffer = 0;
> spi_message_init_with_transfers(&msg, tx, 1);
> ret = spi_sync(ad7949_adc->spi, &msg);
